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ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 146 1 - 888 - 824 - 4184 ia 186e r /ia188e r 16 - bit/ 8 - bit microcontrollers with ram data sheet
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 146 1 - 888 - 824 - 4184 copyright 2013 by innovasic , inc. publi shed by innovasic, inc. 5635 jefferson st. ne, suite a , albuquerque, nm 8710 9 amd , am186, and am188 are trademark s of advanced micro devices, inc . miles? is a trademark of innovasic , inc.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 146 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 8 list of tables ................................ ................................ ................................ ................................ ... 9 conventions ................................ ................................ ................................ ................................ ... 12 acronyms and abbreviations ................................ ................................ ................................ ........ 13 1. introduction ................................ ................................ ................................ ........................... 14 1.1 general description ................................ ................................ ................................ ..... 14 1.2 features ................................ ................................ ................................ ....................... 14 2. packaging, pin descriptions, and physical dimensions ................................ ....................... 15 2.1 packages and pinouts ................................ ................................ ................................ .. 15 2.1.1 ia186er lqfp pack age ................................ ................................ ................ 16 2.1.2 ia188er lqfp package ................................ ................................ ................ 19 2.1.3 lqfp physical dimensions ................................ ................................ ............ 22 2.1.4 ia186er pqfp package ................................ ................................ ................ 23 2.1.5 ia188er pqfp package ................................ ................................ ................ 26 2.1.6 pqfp physical dimensions ................................ ................................ ............ 29 2.2 pin descriptions ................................ ................................ ................................ .......... 30 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16 C a0 address bus (synchronous outputs with tristate) ................................ ................................ ....................... 30 2.2.2 ad15 C ad8 ( ia186er ) address/data bus (level - sensitive synchronous inouts with tristate) ................................ ................................ ......................... 30 2.2.3 ad7 C ad0 address/data bus (level - sensitive synchronous inouts with trista te) ................................ ................................ ................................ ............ 30 2.2.4 ao15 C ao8 ( ia188er ) address - only bus (level - sensitive synchronous outputs with tristate) ................................ ................................ .. 30 2.2.5 ale address latch en able (synchronous output) ................................ ......... 31 2.2.6 ardy asynchronous ready (level - sensitive asynchronous input) ................ 31 2.2.7 bhe_n/aden_n ( ia186er) bu s high enable (synchronous output with tristate)/address enable (input with internal pull - up) ............................ 31 2.2.8 clkouta clock output a (synchronous output) ................................ ............ 32 2.2.9 clkoutb clock output b (synchronous output) ................................ ............ 32 2.2.10 den_n/pio5 data enable strobe (synchronous output with tristate) ............ 32 2.2.11 drq1/pio13 C drq0/pio12 dma requests (synchronous level - sensitive inputs) ................................ ................................ ................................ ............. 32 2.2.12 dt/r_n/pio4 data transmit or receive (synchronous output with tristate) ................................ ................................ ................................ ............ 32 2.2.13 gnd ground ................................ ................................ ................................ .. 32 2.2.14 hlda bus hold acknowledge (synchronous output) ................................ .... 33 2.2.15 hold bus hold request (synchronous level - sensitive input) ....................... 33 2.2.16 int0 maskable interrupt request 0 (asynchronous input) ............................ 33 2.2.17 int1/select_n maskable interrupt request 1/slave select (both are asynchronous inputs) ................................ ................................ ...................... 33
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 146 1 - 888 - 824 - 4184 2.2.18 int2/inta0_n/pio31 maskable interrupt request 2 (asynchronous input)/interrupt acknowl edge 0 (synchronous output) ................................ .. 34 2.2.19 int3/inta1_n/irq maskable interrupt request 3 (asynchronous input)/interrupt acknowledge 1 (synchronous output)/ i nterrupt request (synchronous output) ................................ ................................ ........ 34 2.2.20 int4/pio30 maskable interrupt request 4 (asynchronous input) .................. 34 2.2.21 lcs_n/once0_n lower memory chip select (synchronous o utput with internal pull - up)/once mode request (input) ................................ ...... 35 2.2.22 mcs2_n mcs0_n (pio24, pio15, pio 14) midrange memory chip selects (synchronous outputs with internal pull - up) ................................ ...... 35 2.2.23 mcs3_n/rfsh_n/pio25 midrange memory chip select (synchronous output with internal pull - up)/automatic refresh (synchronous output) ........ 35 2.2.2 4 nmi nonmaskable interrupt (synchronous edge - sensitive input) ................ 35 2.2.25 pcs3_n C pcs0_n (pio19 C pio16) peripheral chip selects 3 C 0 (synchronous outputs) ................................ ................................ ..................... 36 2.2.26 pcs5_n/a1/pio3 peripheral chip select 5 (synchronous output)/latched address bit 1 (synchronous output) ................................ ..... 36 2.2.27 pcs6_n/a2/pio2 peripheral chip select 6 (synchro nous output)/latched address bit 2 (synchronous output) ................................ ...... 36 2.2.28 pio31 C pio0 programmable i/o pins (asynchronous input/output open - drain) ................................ ................................ ................................ ...... 37 2.2.29 rd_n read strobe (synchronous output with tristate) ................................ ... 37 2.2.30 res_n reset (asynchronous level - sensitive input) ................................ ........ 37 2.2.31 rfsh2_n/aden_n ( ia188er) refresh 2 (synchronous output with tristate)/address enable (input with internal pull - up) ................................ .... 37 2.2.32 rxd/pio28 receive data (asynchronous input) ................................ ............ 37 2.2.33 s0_n, s1_n (imdis_n), s0_n (sren_n) bus cycle status (synchronous outputs with tristate) ................................ ................................ ....................... 38 2.2.34 s6/clksel1_n/pio29 bus cycle status bit 6 (synchronous output)/clock divide by 2 (input with internal pull - up) ................................ 38 2.2.35 sclk/pio20 serial clock (synchronous outputs with tristate) ...................... 39 2.2.36 sdata/pio21 serial data (synchronous inout) ................................ .............. 39 2.2.37 sden1/pio23 C sden0/pio22 serial data enables (synchronous outputs with tristate) ................................ ................................ ....................... 39 2.2.38 srdy/pio6 synchronous ready (synchronous level - sensitive input) ............ 39 2.2.39 tmrin0/pio11 timer input 0 (synchronous edge - sensitive input) ................ 39 2.2.40 tmrin1/pio0 timer input 1 (synchronous edge - sensitive input) .................. 39 2.2.41 tmrout0/pio10 timer output 0 (synchronous output) ................................ . 40 2.2.42 tmrout1/pio1 timer output 1 (synchronous output) ................................ ... 40 2.2.43 txd/pio27 transmit data (asynchronous output) ................................ ......... 40 2.2.44 ucs_n/once1_n upper memory chip select (synchronous output)/once mode request 1 (input with internal pull - up) ........................ 40
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 146 1 - 888 - 824 - 4184 2.2.45 uzi_n/clksel2_n/pio26 uppe r zero indicate (synchronous output)/clock select 2 (input, pullup) ................................ .............................. 40 2.2.46 v cc power supply (input) ................................ ................................ .............. 40 2.2.47 whb_n ( ia186er ) w rite high byte (synchronous output with tristate) ................................ ................................ ................................ ............ 41 2.2.48 wlb_n/wb_n write low byte ( ia186er ) (synchronous output with tristate)/write byte ( ia188er) (synchronous output with tristate) ............... 41 2.2.49 wr_n write strobe (synchronous output) ................................ .................... 41 2.2.50 x1 crystal input (input) ................................ ................................ ............... 41 2.2.51 x2 crystal input (input) ................................ ................................ ............... 41 2.3 pins used by emulators ................................ ................................ .............................. 41 3. maximum ratings, thermal characteristics, and dc parameters ................................ ....... 43 4. device architecture ................................ ................................ ................................ .............. 44 4.1 bus interface and control ................................ ................................ ........................... 44 4.2 clock and power management ................................ ................................ ................... 46 4.3 system clocks ................................ ................................ ................................ ............. 46 4.4 power - save mode ................................ ................................ ................................ ....... 47 4.5 initialization and reset ................................ ................................ ................................ 4 7 4.6 reset configuration register ................................ ................................ ...................... 47 4.7 chip selects ................................ ................................ ................................ ................. 47 4.8 chip - select timing ................................ ................................ ................................ ... 47 4.9 ready - and wait - state programming ................................ ................................ .......... 48 4.10 chip select overl ap ................................ ................................ ................................ .... 48 4.11 upper memory chip select ................................ ................................ ......................... 49 4.12 low memory chip select ................................ ................................ ........................... 49 4.13 midrange memory chip selects ................................ ................................ ................. 49 4.14 peripheral chip selects ................................ ................................ ............................... 50 4.15 refresh control ................................ ................................ ................................ ........... 50 4.16 interrupt control ................................ ................................ ................................ .......... 50 4.16.1 interrupt types ................................ ................................ ................................ 51 4.17 timer control ................................ ................................ ................................ .............. 52 4.18 direct memory access (dma) ................................ ................................ ................... 53 4.19 dma operation ................................ ................................ ................................ ........... 53 4.20 dma channel control registers ................................ ................................ ................ 54 4.21 dma priority ................................ ................................ ................................ .............. 54 4.22 asynchronous serial port ................................ ................................ ............................ 54 4.23 synchro nous serial port ................................ ................................ .............................. 55 4.24 programmable i/o (pio) ................................ ................................ ............................. 55 4.25 watchdog timer ................................ ................................ ................................ .......... 57 4.26 internal memory ................................ ................................ ................................ .......... 58 5. peripheral architecture ................................ ................................ ................................ ......... 58 5.1 control and registers ................................ ................................ ................................ .. 58 5.1.1 relreg (0feh) ................................ ................................ .............................. 60
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 146 1 - 888 - 824 - 4184 5.1.2 rescon (0f6h) ................................ ................................ .............................. 60 5.1.3 prl (0f4h) ................................ ................................ ................................ ...... 61 5.1.4 pdcon (0f0h) ................................ ................................ ................................ 61 5.1.5 wdtcon (0e6h) ................................ ................................ ........................... 62 5.1.6 edram (0e4h) ................................ ................................ .............................. 63 5.1.7 cdram (0e2h) ................................ ................................ .............................. 64 5.1.8 mdram (0e0h) ................................ ................................ ............................. 64 5.1.9 d1con (0dah) and d0con (0cah) ................................ ............................... 64 5.1.10 d1tc (0d8h) and d0tc (0c8h) ................................ ................................ ..... 66 5.1.11 d1dsth (0d6h) and d0dsth (0c6h) ................................ ........................... 67 5.1.12 didst l (0d4h) and d0dstl (0c4h) ................................ ............................ 67 5.1.13 d1srch (0d2h) and d0srch (0c2h) ................................ ........................... 67 5.1.14 d1srcl (0d0h) and d0srcl (0c0h) ................................ ............................ 68 5.1.15 imcs (0ach) ................................ ................................ ................................ ... 68 5.1.16 mpcs (0a8h) ................................ ................................ ................................ .. 69 5.1.17 mmcs (0a6h) ................................ ................................ ................................ . 70 5.1.18 pacs (0a4h) ................................ ................................ ................................ ... 71 5.1.19 lmcs (0a2h) ................................ ................................ ................................ .. 73 5.1.20 umcs (0a0h) ................................ ................................ ................................ .. 74 5.1.21 spbaud (088h) ................................ ................................ ............................. 75 5.1.22 sprd (086h) ................................ ................................ ................................ ... 76 5.1.23 sptd (084h) ................................ ................................ ................................ ... 76 5.1.24 spsts (082h) ................................ ................................ ................................ . 77 5.1.25 spct (080h) ................................ ................................ ................................ ... 78 5.1.26 pdata1 (07ah) and pdata0 (074h) ................................ ........................... 80 5.1.27 pdir1 (078h) and pdir0 (072h) ................................ ................................ ... 82 5.1.28 piomode1 (076h) and piomode0 (070h) ................................ ................. 82 5.1.29 t1con (05eh) and t0con (056h) ................................ ................................ 83 5.1.30 t2con (066h) ................................ ................................ ................................ 84 5.1.31 t2compa (062h), t1compb (05ch), t1comp a (05ah), t0compb (054h), and t0compa (052h) ................................ ................... 85 5.1.32 t2cnt (060h), t1cnt (058h), and t0cnt (050h) ................................ ..... 86 5.1.33 spicon (044h) (maste r mode) ................................ ................................ ..... 86 5.1.34 wdcon (042h) (master mode) ................................ ................................ .... 87 5.1.35 i4con (040h) (master mode) ................................ ................................ ........ 87 5.1.36 i3con (03eh) and i2con (03ch) (master mode) ................................ ......... 88 5.1.37 i1con (03ah) and i0con (038h) (master mode) ................................ ......... 88 5.1. 38 tcucon (032h) (master mode) ................................ ................................ ... 89 5.1.39 t2intcon (03ah), t1intcon (038h), and t0intcon (032h) (slave mode) ................................ ................................ ................................ .. 90 5.1.40 dma1con (036 h) and dma0con (034h) (master mode) ......................... 90 5.1.41 dma1con (036h) and dma0con (034h) (slave mode) ........................... 90 5.1.42 intsts (030h) (master mode) ................................ ................................ ...... 91
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 146 1 - 888 - 824 - 4184 5.1.43 intsts (030h) (slave mode) ................................ ................................ ........ 91 5.1.44 reqst (02eh) (master mode) ................................ ................................ ....... 92 5.1.45 reqst (02eh) (slave mode) ................................ ................................ ......... 93 5.1.46 inserv (02ch) (master mode) ................................ ................................ ..... 93 5.1.47 inserv (02ch) (slave mode) ................................ ................................ ........ 94 5.1.48 primsk (02ah) (master and slave mode) ................................ .................... 95 5.1.49 imask (028h) (master mode) ................................ ................................ ....... 95 5.1.50 imask (028h) (slave mode) ................................ ................................ ......... 96 5.1.51 pollst (026h) (master mode) ................................ ................................ ..... 97 5.1.52 poll (024h) (master mode) ................................ ................................ .......... 97 5.1.53 eoi (022h) e nd - o f - i nterrupt register (master mode) ................................ .. 98 5.1.54 eoi (022h) specific e nd - o f - i nterrupt register (slave mode) ...................... 98 5.1.55 intvec (020h) int errupt vec tor register (slave mode) .............................. 99 5.1.56 ssr (018h) ................................ ................................ ................................ ...... 99 5.1.57 ssd0 (016h) and ssd1 (014h) ................................ ................................ ....... 99 5.1.58 ssc (012h) ................................ ................................ ................................ .... 100 5.1.59 sss (010h) ................................ ................................ ................................ .... 100 5.2 reference documents ................................ ................................ ............................... 101 6. ac specifications ................................ ................................ ................................ ............... 101 7. instruction set summary table ................................ ................................ .......................... 130 7.1 key to abbreviations used in instruction set summary table ................................ 140 7.1.1 operand address byte ................................ ................................ .................. 140 7.1.2 modifier field ................................ ................................ ............................... 140 7.1.3 auxiliary field ................................ ................................ .............................. 141 7.1.4 r/m field ................................ ................................ ................................ ........ 141 7.1.5 displacement ................................ ................................ ................................ 141 7.1.6 immediate bytes ................................ ................................ ........................... 141 7.1.7 segment override prefix ................................ ................................ .............. 141 7.1.8 segment register ................................ ................................ .......................... 142 7.2 explanation of notation used in instruction set summary table ............................ 142 7.2.1 opcode ................................ ................................ ................................ .......... 142 7.2.2 flags affected after instruction ................................ ................................ ... 143 8. innovasic/amd part number cross - reference table ................................ ....................... 144 9. revision history ................................ ................................ ................................ ................. 145 10. for additional information ................................ ................................ ................................ . 146
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 146 1 - 888 - 824 - 4184 list of figures figure 1 . ia186er lqfp package diagram ................................ ................................ ................ 16 figure 2 . ia188er lqfp package diagram ................................ ................................ ................ 19 figure 3 . lqfp package dimensions ................................ ................................ ........................... 22 figure 4 . ia186er pqfp package diagram ................................ ................................ ................ 23 figure 5 . ia188er pqfp package diagram ................................ ................................ ................ 26 figure 6 . pqfp package dimensions ................................ ................................ ........................... 29 figure 7 . functional block diagram ................................ ................................ ............................ 45 figure 8. crystal configuration ................................ ................................ ................................ .... 46 figure 10 . read cycle ................................ ................................ ................................ ................. 109 figure 11 . multiple read cycles ................................ ................................ ................................ 110 figure 12 . write cycle ................................ ................................ ................................ ................ 112 figure 13 . multiple write cycles ................................ ................................ ............................... 113 fi gure 14 . psram read cycle ................................ ................................ ................................ .. 115 figure 15 . psram write cycle ................................ ................................ ................................ . 11 7 figure 16 . psram refresh cycle ................................ ................................ .............................. 119 figure 17 . internal ram show read cycle ................................ ................................ ............... 120 figure 18 . interrupt acknowledge cycle ................................ ................................ .................... 121 figure 19 . software halt cycle ................................ ................................ ................................ .. 123 figure 20 . clock active mode ................................ ................................ ................................ . 124 figure 21 . clock power - save mode ................................ ................................ ........................ 124 figure 22 . srdy synchronous ready ................................ ................................ ........................ 125 figure 23 . ardy asynchronous ready ................................ ................................ ...................... 126 figure 24 . perip herals ................................ ................................ ................................ ................. 126 figure 25 . reset 1 ................................ ................................ ................................ ....................... 127 figure 26 . reset 2 ................................ ................................ ................................ ....................... 127 figure 2 7 . bus hold entering ................................ ................................ ................................ ..... 128 figure 28 . bus hold leaving ................................ ................................ ................................ ...... 128 figure 29 . synchronous serial interface ................................ ................................ ..................... 129
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 146 1 - 888 - 824 - 4184 list of tables table 1 . ia186er lqfp numeric pin listing ................................ ................................ ............. 17 table 2 . ia186er lqfp alphabetic pin listing ................................ ................................ ......... 18 table 3 . ia188er lqfp numeric pin listing ................................ ................................ ............. 20 table 4 . ia188er lqfp a lphabetic pin listing ................................ ................................ ......... 21 table 5 . ia186er pqfp numeric pin listing ................................ ................................ ............. 24 table 6 . ia186er pqfp alphabetic pin listing ................................ ................................ ......... 25 table 7 . ia188er pqfp numeric pin listing ................................ ................................ ............. 27 table 8 . ia188er pqfp alphabetic pin listing ................................ ................................ ......... 28 table 9 . bus cycle types for bhe_n and ad0 ................................ ................................ ............... 31 table 10 . bus cycle types for s2_n, s1_n, and s0_n ................................ ................................ ... 38 table 11. ia186er and ia188er absolute maximum ratings ................................ .................. 43 table 12. ia186er and ia188er thermal characteristics ................................ ......................... 43 table 13. dc character istics over industrial operating ranges ................................ ................. 43 table 14. interrupt types ................................ ................................ ................................ .............. 51 table 15. default status of pio pins at reset ................................ ................................ .............. 56 table 16. peripheral control registers ................................ ................................ ......................... 59 table 17. peripheral control block rel ocation reg ister ................................ .............................. 60 table 18. reset configuration reg ister ................................ ................................ ........................ 60 table 19. p rocessor r elease l evel register ................................ ................................ ................. 61 table 20. p ower - save control register ................................ ................................ ........................ 61 table 21. w atchdog t imer con trol register ................................ ................................ ................ 62 table 22. e nable d ynamic ram refresh control register ................................ ......................... 63 table 23. c ount for dynamic ram refresh control register ................................ .................... 64 table 24. m emory partition for d ynamic ram refresh control regis ter ................................ . 64 table 25. dma control registers ................................ ................................ ................................ 64 table 26. dma transfer count registers ................................ ................................ .................... 66 table 27. d ma d e st ination address high register ................................ ................................ .... 67 table 28. d ma d e st ination address l ow register ................................ ................................ ..... 67 table 29 . d ma s ou rc e address h igh register ................................ ................................ ............ 68 table 30. d ma s ou rc e address l ow register ................................ ................................ ............ 68 table 31. internal memory chip select regist er ................................ ................................ ......... 68 table 32. mcs and pcs auxiliar y register ................................ ................................ ................ 69 table 33. m idrange m emory c hip s elect register ................................ ................................ ...... 70 table 34. p eripher a l c hip s elec t register ................................ ................................ .................... 72 table 35. low - memory chip select register ................................ ................................ .............. 73 tab le 36. u pper - m emor y c hip s elect register ................................ ................................ ........... 74 table 37. baud rates ................................ ................................ ................................ .................... 75 table 38. s erial p ort baud rate divisor registers ................................ ................................ ....... 76 table 39. s erial p ort r eceive data register ................................ ................................ ................. 76 table 40. s erial p ort t ransmit data register ................................ ................................ ............... 77 table 41. s erial p ort st atu s register ................................ ................................ ............................ 77
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 146 1 - 888 - 824 - 4184 table 42. s erial p ort control register ................................ ................................ .......................... 78 table 43. pio pin as signments ................................ ................................ ................................ .... 80 table 44. pdata 0 ................................ ................................ ................................ ...................... 81 table 45. pdata 1 ................................ ................................ ................................ ...................... 81 table 46. pio mode and pio direction settings ................................ ................................ ......... 82 table 47. pdir0 ................................ ................................ ................................ ........................... 82 table 48. pdir1 ................................ ................................ ................................ ........................... 82 table 49. piomode0 ................................ ................................ ................................ .................. 82 table 50. pmode1 ................................ ................................ ................................ ...................... 83 table 51. t ime r 0 and t ime r 1 mode and con trol registers ................................ ....................... 83 table 52. t ime r 2 mode and con trol registers ................................ ................................ ........... 84 table 53. t ime r maxcount com pare registers ................................ ................................ ............ 85 table 54. t imer c ou nt registers ................................ ................................ ................................ .. 86 table 55. s erial p ort interrupt con trol registers ................................ ................................ ......... 86 table 56. watchdog tim er interrupt con trol register ................................ ................................ . 87 table 57. i nt 4 con trol register ................................ ................................ ................................ .. 87 table 58. i nt 2 / i nt 3 con trol register ................................ ................................ ........................ 88 table 59. i nt 0 / i nt 1 con trol register ................................ ................................ ........................ 89 table 60. t imer c ontrol u nit interrupt con trol register ................................ ............................. 89 table 61. t imer int errupt con trol register ................................ ................................ .................. 90 table 62. dma and int errupt con trol register (master mode) ................................ ................... 90 table 63. dma and int errupt con trol register (slave mode) ................................ ..................... 91 table 64. int errupt st atu s register (master mode) ................................ ................................ ...... 91 table 65. int errupt st atu s register (slave mode) ................................ ................................ ........ 92 table 66. interrupt req ue st register (master mode) ................................ ................................ ... 92 table 67. interrupt req ue st register (sla ve mode) ................................ ................................ ..... 93 table 68. in - serv ice register (master mode) ................................ ................................ .............. 94 table 69. in - serv ice register (slave mode) ................................ ................................ ................. 94 table 70. pri ority m a sk register ................................ ................................ ................................ .. 95 table 71. i nterrupt mask register (master mode) ................................ ................................ .... 96 t able 72. i nterrupt mask register (slave mode) ................................ ................................ ....... 96 table 73. poll st atus register ................................ ................................ ................................ ... 97 table 74. poll register ................................ ................................ ................................ .................. 98 table 75. e nd - o f - i nterrupt register ................................ ................................ .............................. 98 table 76. specific e nd - o f - i nterrupt register ................................ ................................ ................ 98 table 77. int errupt vec tor register ................................ ................................ .............................. 99 table 78. s ynchronous s erial r eceive register ................................ ................................ ........... 99 table 79. s ynchronous s erial trans mit registers ................................ ................................ ........ 99 table 80. s ynchronous s erial control registers ................................ ................................ ........ 100 table 81. s ynchronous s erial status registers ................................ ................................ ........... 100 table 82. ac characteristics over industrial operating ranges (50 mhz) .............................. 102 table 83. alphabetic key to waveform parameters ................................ ................................ .. 105 table 84. numeric key to waveform parameters ................................ ................................ ...... 107
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 146 1 - 888 - 824 - 4184 table 85. read cycle timing ................................ ................................ ................................ ..... 111 table 86. write cycle timing ................................ ................................ ................................ .... 114 table 87. psram read cycle timing ................................ ................................ ....................... 116 table 88. psram write cycle timing ................................ ................................ ...................... 118 table 89. psram refresh cycle ................................ ................................ ............................... 119 table 91. interrupt acknowledge cycle timing ................................ ................................ ........ 122 table 92. software halt cycle timing ................................ ................................ ....................... 123 table 93. clock timing ................................ ................................ ................................ .............. 125 table 94. ready and peripheral timing ................................ ................................ ..................... 127 table 95. reset and bus hold timing ................................ ................................ ........................ 129 table 96. synchronous serial interface timing ................................ ................................ ......... 130 table 97. instruction set summary ................................ ................................ ............................ 130 table 98. innovasic/amd part number cross - reference ................................ ......................... 144 table 99. revision history ................................ ................................ ................................ ......... 1 45
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 146 1 - 888 - 824 - 4184 conventions arial bold designates headings, figure captions, and table captions. blue designates hyperlinks (pdf copy only). italics designates emphasis or caution related to n earby information. italics is also used to designate variables, refer to related documents, and to differentiate terms from other common words (e.g., during refresh cycles, the a and ad bus es may not have the same address during the address phase of the ad bus cycle. the hold latency time [time between the hold and hlda ] depends on the current processor activity when the hold is received. ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 146 1 - 888 - 824 - 4184 acronyms and abbreviations amd advanced micro devices bic bus i nterface and control cdram c ount for dynamic ram csc chip selects and control da disable address dma direct memory access eoi end of interrupt isr interrupt service routine lmcs low - memory chip select lqfp low - profile quad flat package mc maximum count mdr am m emory partition for d ynamic ram miles ? managed ic lifetime extension system mmcs m idrange m emory c hip s elect nmi nonmaskable interrupt pcb peripheral control block pio programmable i/o pll phase - lock - loop por power - on reset pqfp plastic quad flat packa ge psram pseudo - static ram rcu refresh control unit rohs restriction of hazardous substances sfnm special fully nested mode uart universal asynchronous receiver - transmitter umcs upper memory chip select
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 146 1 - 888 - 824 - 4184 1. introduction the ia186er/ia188er is a form, fit, and function replacement for the original advanced micro devices am186er/am188er family of microcontrollers. innovasic produces replacement ics using its miles tm , or managed ic lifetime extension system cloning technology. this technology produces replaceme nt ics far more complex than emulation while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the undocumented features are duplicated . 1.1 general description the ia186er/ia188er family of microcontrollers replaces obsolete am186er/188er devices, allowing customers to retain existing board designs, software compilers/assemblers and emul ation tools, thereby avoiding expensive redesign efforts. the ia186er/ia188er microcontrollers are an upgrade for the 80c186/80c188 microcontroller designs, with integrated peripherals to provide increased functionality and reduce system costs. the innova sic devices are created to satisfy requirements of embedded products designed for telecommunications, office automation and storage, and industrial controls . 1.2 features pin - for - pin compatible with am186er/am188er devices all features are retained, including: o a phase - lock loop (pll) allowing same crystal/system clock frequency o 8086/8088 instruction set with additional 186 instruction set extensions o programmable interrupt controller o two direct memory access (dma) channels o three 16 - bit timers o internal 32k bytes of memory o programmable chip select logic and wait - state generator o dedicated watchdog timer o independent asynchronous serial port (uart) ? dma capability ? hardware flow control ? 7 - , 8 - , or 9 - bit data capability synchronous serial port o half duplex bidirectional d ata transfer up to 32 programmable i/o pins (pio) pseudo - static/dynamic ram controller fully static cmos design 50 mhz operation at industrial operating conditions +3.3 vdc power supply - 40c to +85c operating temperature
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 146 1 - 888 - 824 - 4184 2. packaging , pin descriptions, and ph ysical dimensions information on the packages and pin descriptions for the ia 186er and the ia 188er is provided separately. refer to sections, figures, and tables for information on the device of interest. innovasics part number for these devices is mark ed as 18x to indicate the same device will be ordered for the 186 and 188 versions of each particular package style (see section 8) . please refer to this data sheet for specific use of the pins for the 186 and 188 versions . please also note that t he data bus width of the ia18xer is selectable between 16 - bit (ia186er) or 8 - bit (ia188er) upon powerup. for 8 - bit operation tie the whb_n pin to ground. reference pin descriptions appropriate for the selected strapping option. 2.1 packages and pinouts the innovasi c ia 186er and ia 188er microcontroller is available in the following packages: 100 - pin low - profile quad flat package ( l qfp), equivalent to original t qfp package 100 - pin plastic quad flat package (pqfp), equivalent to original pqfp package
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 146 1 - 888 - 824 - 4184 2.1.1 ia 186er l qfp pac kage the pinout for the ia 186er lqfp package is as shown in figure 1. the corresponding pinout is provided in tables 1 and 2. figure 1 . ia 186er l qfp package diagram i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 m c s 0 _ n / p i o 1 4 d e n _ n / p i o 5 d t / r _ n / p i o 4 n m i s r d y / p i o 6 h o l d h l d a w l b _ n w h b _ n g n d a 0 a 1 v c c a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 d r q 0 / p i o 1 2 d r q 1 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / p i o 1 8 p c s 3 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q a d 0 a d 8 a d 1 a d 9 a d 2 a d 1 0 a d 3 a d 1 1 a d 4 a d 1 2 a d 5 g n d a d 1 3 a d 6 v c c a d 1 4 a d 7 a d 1 5 s 6 / c l k s e l 1 _ n / p i o 2 9 u z i _ n / c l k s e l 2 _ n / p i o 2 6 t x d / p i o 2 7 r x d / p i o 2 8 s d a t a / p i o 2 1 s d e n 1 / p i o 2 3 s d e n 0 / p i o 2 2 s c l k / p i o 2 0 b h e _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n / i m d i s _ n s 0 _ n / s r e n _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 i a 1 8 6 e r l q f p
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 146 1 - 888 - 824 - 4184 table 1 . ia 186er l qfp numeric pin listing pin name pin name pin name 1 ad0 35 gnd 68 hold 2 ad8 36 x1 69 srdy/pio6 3 ad1 37 x2 70 nmi 4 ad9 38 v cc 71 dt/r_n/pio4 5 ad2 39 clkouta 72 den_n/pio5 6 ad10 40 clkoutb 73 mcs0_n/pio14 7 ad3 41 gnd 74 mcs1_n/pio15 8 ad11 42 a19/pio9 75 int4/pio30 9 ad4 43 a18/pio8 76 int3/inta1_n/irq 10 ad12 44 v cc 77 int2/inta0_n/pio31 11 ad5 45 a17/pio7 78 int1/select_n 12 gnd 46 a16 79 int0 13 ad13 47 a15 80 ucs_n/once1_n 14 ad6 48 a14 81 lc s_n/once0_n 15 v cc 49 a13 82 pcs6_n/a2/pio2 16 ad14 50 a12 83 pcs5_n/a1/pio3 17 ad7 51 a11 84 v cc 18 ad15 52 a10 85 pcs3_n/pio19 19 s6/clk sel1 _n /pio29 53 a9 86 pcs2_n/pio18 20 uzi_n/ clksel2 _n / pio26 54 a8 87 gnd 21 txd/pio27 55 a7 88 pc s1_n/pio17 22 rxd/pio28 56 a6 89 pcs0_n/pio16 23 sdata/pio21 57 a5 90 v cc 24 sden1/pio23 58 a4 91 mcs2_n/pio24 25 sden0/pio22 59 a3 92 mcs3_n/rfsh_n/pio25 26 sclk/pio20 60 a2 93 gnd 27 bhe_n/aden_n 61 v cc 94 res_n 28 wr_n 62 a1 95 tmri n1/pio0 29 rd_n 63 a0 96 tmrout1/pio1 30 ale 64 gnd 97 tmrout0/pio10 31 ardy 65 whb_n 98 tmrin0/pio11 32 s2_n 66 wlb_n 99 drq1/pio13 33 s1_n /imdis_n 67 hlda 100 drq0/pio12 34 s0_n /sren_n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 146 1 - 888 - 824 - 4184 table 2 . ia 186er l qfp alphabetic pin listing name pin name pin name pin a0 63 ad14 16 pcs3_n/pio19 85 a1 62 ad15 18 pcs5_n/a1/pio3 83 a2 60 ale 30 pcs6_n/a2/pio2 82 a3 59 ardy 31 rd_n 29 a4 58 bhe_n/aden_n 27 res_n 94 a5 57 clkouta 39 rxd/pio28 22 a6 56 clkoutb 40 s0_n /sren_n 34 a7 55 den_n/pio5 72 s1_n /imdis_n 33 a8 54 drq0/pio12 100 s2_n 32 a9 53 drq1/pio13 99 s6/clksel1 _n /pio29 19 a10 52 dt/r_n/pio4 71 sclk/pio20 26 a11 51 gnd 12 sdata/pio21 23 a12 50 gnd 35 sden0/pio22 25 a13 49 gnd 41 sden1/pio23 24 a14 48 gnd 64 srdy/pio6 69 a15 47 gnd 87 tmrin0/pio11 98 a16 46 gnd 93 tmrin1/pio0 95 a17/pio7 45 hlda 67 tmrout0/pio10 97 a18/pio8 43 hold 68 tmrout1/pio1 96 a19/pio9 42 int0 79 txd/pio27 21 ad0 1 int1/select_n 78 ucs_n/once1_n 80 ad1 3 int2/inta0_n/pio31 77 uzi_n/ clksel2 _n / pio26 20 ad2 5 int3/inta1_n/irq 76 v cc 15 ad3 7 int4/pio30 75 v cc 38 ad4 9 lcs_n/once0_n 81 v cc 44 ad5 11 mcs0_n/pio14 73 v cc 61 ad6 14 mcs1_n/pio15 74 v cc 84 ad7 17 mcs2_n/pio24 91 v cc 90 ad8 2 mcs3_n/rfsh_n/pio25 92 whb_n 65 ad9 4 nmi 70 wlb_n 66 ad10 6 pcs0_n/pio16 89 wr_n 28 ad11 8 pcs1_n / pio 17 88 x1 36 ad12 10 pcs2_n/pio18 86 x2 37 ad13 13
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 146 1 - 888 - 824 - 4184 2.1.2 ia 188er l qfp package the pinout for the ia 188er lqfp package is as shown in figure 2. the corresponding pinout is provided in tables 3 and 4. figure 2 . ia 188er l qfp package diagram i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 m c s 0 _ n / p i o 1 4 d e n _ n / p i o 5 d t / r _ n / p i o 4 n m i s r d y / p i o 6 h o l d h l d a w b _ n g n d g n d a 0 a 1 v c c a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 d r q 0 / p i o 1 2 d r q 1 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / p i o 1 8 p c s 3 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q a d 0 a o 8 a d 1 a o 9 a d 2 a o 1 0 a d 3 a o 1 1 a d 4 a o 1 2 a d 5 g n d a o 1 3 a d 6 v c c a o 1 4 a d 7 a o 1 5 s 6 / c l k s e l 1 _ n / p i o 2 9 u z i _ n / c l k s e l 2 _ n / p i o 2 6 t x d / p i o 2 7 r x d / p i o 2 8 s d a t a / p i o 2 1 s d e n 1 / p i o 2 3 s d e n 0 / p i o 2 2 s c l k / p i o 2 0 r f s h 2 _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n / i m d i s _ n s 0 _ n / s r e n _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 i a 1 8 8 e r l q f p
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 146 1 - 888 - 824 - 4184 table 3 . ia 188er l qfp n umeric pin listing pin name pin name pin name 1 ad0 35 gnd 68 hold 2 ao8 36 x1 69 srdy/pio6 3 ad1 37 x2 70 nmi 4 ao9 38 v cc 71 dt/r_n/pio4 5 ad2 39 clkouta 72 den_n/pio5 6 ao10 40 clkoutb 73 mcs0_n/pio14 7 ad3 41 gnd 74 mcs1_n/pio15 8 ao11 42 a19/pio9 75 int4/pio30 9 ad4 43 a18/pio8 76 int3/inta1_n/irq 10 ao12 44 v cc 77 int2/inta0_n/pio31 11 ad5 45 a17/pio7 78 int1/select_n 12 gnd 46 a16 79 int0 13 ao13 47 a15 80 ucs_n/once1_n 14 ad6 48 a14 81 lcs_n/once0_n 15 v c c 49 a13 82 pcs6_n/a2/pio2 16 ao14 50 a12 83 pcs5_n/a1/pio3 17 ad7 51 a11 84 v cc 18 ao15 52 a10 85 pcs3_n/pio19 19 s6/clk sel1 _n /pio29 53 a9 86 pcs2_n/pio18 20 uzi_n/ clksel2 _n / pio26 54 a8 87 gnd 21 txd/pio27 55 a7 88 pcs1_n/pio17 22 rxd /pio28 56 a6 89 pcs0_n/pio16 23 sdata/pio21 57 a5 90 v cc 24 sden1/pio23 58 a4 91 mcs2_n/pio24 25 sden0/pio22 59 a3 92 mcs3_n/rfsh_n/pio25 26 sclk/pio20 60 a2 93 gnd 27 rfsh2_n/aden_n 61 v cc 94 res_n 28 wr_n 62 a1 95 tmrin1/pio0 29 rd_n 63 a0 96 tmrout1/pio1 30 ale 64 gnd 97 tmrout0/pio10 31 ardy 65 gnd 98 tmrin0/pio11 32 s2_n 66 wb_n 99 drq1/pio13 33 s1_n /imdis_n 67 hlda 100 drq0/pio12 34 s0_n /sren_n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 146 1 - 888 - 824 - 4184 table 4 . ia 188er l qfp alphabetic pin listing name pin name pin name pin a0 63 ao13 13 pcs3_n/pio19 85 a1 62 ao14 16 pcs5_n/a1/pio3 83 a2 60 ao15 18 pcs6_n/a2/pio2 82 a3 59 ardy 3 1 rd_n 29 a4 58 clkouta 39 res_n 94 a5 57 clkoutb 40 rfsh2_n/aden_n 27 a6 56 den_ n /pio5 72 rxd/pio28 22 a7 55 drq0/pio12 100 s0_n /sren_n 34 a8 54 drq1/pio13 99 s1_n /imdis_n 33 a9 53 dt/r_n/pio4 71 s2_n 32 a10 52 gnd 12 s6 /clk sel1_n /pio29 19 a11 51 gnd 35 sclk/pio20 26 a12 50 gnd 41 sdata/pio21 23 a13 49 gnd 64 sden0/pio22 25 a14 48 gnd 65 sden1/pio23 24 a15 47 gnd 87 srdy/pio6 69 a16 46 gnd 93 tmrin0/pio11 98 a17/pio7 45 hlda 67 tmrin1/pio0 95 a18/pio8 43 hold 68 tmrout0/pio10 97 a19/pio9 42 int0 79 tmrout1/pio1 96 ad0 1 int1/select_n 78 txd/pio27 21 ad1 3 int2/inta0_n/pio31 77 ucs_n/once1_n 80 ad2 5 int3/inta1_n/irq 76 uzi_n/ clksel2_n/ pio26 20 ad3 7 int4/pio30 75 v cc 15 ad4 9 lcs_n/once0_n 81 v cc 38 ad5 11 mcs0_n/pio14 73 v cc 44 ad6 14 mcs1_n/pio15 74 v cc 61 ad7 17 mcs2_n/pio24 91 v cc 84 ale 30 mcs3_n/rfsh_n/pio25 92 v cc 90 ao8 2 nmi 70 wb_n 66 ao9 4 pcs0_n/pio16 89 wr_n 28 ao10 6 pcs1_n/pio17 88 x1 36 ao11 8 pcs2_n/pio18 86 x2 37 ao12 10
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 146 1 - 888 - 824 - 4184 2.1.3 l qfp physical dimensions the physical dimensions for the l qfp a re as shown in figure 3. figure 3 . l qfp package dimensions legend: symbol millimeter inch min nom max min nom max a C C 1. 6 0 C C 0.0 63 a1 0.0 5 C 0.15 0.0 0 2 C 0.006 a2 1.35 1. 4 0 1. 4 5 0.0 53 0.0 55 0.0 57 b 0.17 0.2 2 0.27 0.007 0.00 9 0.011 c 0.09 C 0.20 0.004 C 0.008 d 15.85 16.00 16 .15 0.624 0.630 0.636 d 1 13.90 14.00 14.10 0.547 0.551 0.555 e 15.85 16.00 16.15 0.624 0.630 0.636 e 1 13.90 14.00 14.10 0.547 0.551 0.555 e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.0 39 ref r 1 0.08 C C 0.003 C C r 2 0.08 C 0.2 0 0.003 C 0.008 s 0.2 0 C C 0.008 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2 11 12 13 11 12 13 3 11 12 13 11 12 13 note : control dimensions are in millimeters.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 146 1 - 888 - 824 - 4184 2.1.4 ia 186er pqfp package the pinout for the ia 186er pqfp package is as show n in figure 4. the corresponding pinout is provided in tables 5 and 6. figure 4 . ia 186er pqfp package diagram s d a t a / p i o 2 1 r x d / p i o 2 8 t x d / p i o 2 7 u z i _ n / c l k s e l 2 _ n / p i o 2 6 s 6 / c l k s e l 1 _ n / p i o 2 9 a d 1 5 a d 7 a d 1 4 v c c a d 6 a d 1 3 g n d a d 5 a d 1 2 a d 4 a d 1 1 a d 3 a d 1 0 a d 2 a d 9 i a 1 8 6 e s t q f p a d 1 a d 8 a d 0 d r q 0 / p i o 1 2 d r q 1 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / p i o 1 8 p c s 3 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 s d e n 1 / p i o 2 3 s d e n 0 / p i o 2 2 s c l k / p i o 2 0 b h e _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n / i m d i s _ n s 0 _ n / s r e n _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 v c c a 1 a 0 g n d w h b _ n w l b _ n h l d a h o l d s r d y / p i o 6 n m i d t / r _ n / p i o 4 d e n _ n / p i o 5 m c s 0 _ n / p i o 1 4 i a 1 8 6 e r p q f p ?
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 146 1 - 888 - 824 - 4184 table 5 . ia 186er pqfp numeric pin listing pin name pin name pin name 1 sden1/pio23 35 a4 68 mcs2_n/pio24 2 sden0 /pio22 36 a3 69 mcs3_n/rfsh_n/pio25 3 sclk/pio20 37 a2 70 gnd 4 bhe_n/aden_n 38 v cc 71 res_n 5 wr_n 39 a1 72 tmrin1/pio 0 6 rd_n 40 a0 73 tmrout1/pio1 7 ale 41 gnd 74 tmrout0/pio10 8 ardy 42 whb_n 75 tmrin0/pio11 9 s2_n 43 wlb_n 76 drq1/pio13 10 s1_n /imdis_n 44 hlda 77 drq0/pio12 11 s0_n /sren_n 45 hold 78 ad0 12 gnd 46 srdy/pio6 79 ad8 13 x1 47 nmi 80 ad1 14 x2 48 dt/r_n/pio4 81 ad9 15 v cc 49 den_n/pio5 82 ad2 16 clkouta 50 mcs0_n/pio14 83 ad10 17 clkoutb 51 mcs1_n/pio15 84 ad3 18 gnd 52 int4/pio30 85 ad11 19 a19/pio 9 53 int3/inta1_n/irq 86 ad4 20 a18/pio8 54 int2/inta0_n/pio31 87 ad12 21 v cc 55 int1/select_n 88 ad5 22 a17/pio7 56 int0 89 gnd 23 a16 57 ucs_n/once1_n 90 ad13 24 a15 58 lcs_n/once0_n 91 ad6 25 a14 59 pcs6_n/a2/pio2 92 v cc 26 a13 60 pcs5_n/a1/pio3 93 ad14 27 a12 61 v cc 94 ad7 28 a11 62 pcs3_n/pio19 95 ad15 29 a10 63 pcs2_n/pio18 96 s6/clk sel1 _n/pio29 30 a9 6 4 gnd 97 uzi_n/ clksel2_n/ pio26 31 a8 65 pcs1_n/pio17 98 txd/pio27 32 a7 66 pcs0_n/pio16 99 rxd/pio28 33 a6 67 v cc 100 sdata/pio21 34 a5
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 146 1 - 888 - 824 - 4184 table 6 . ia 186er pqfp alphabetic pin listing name pin name pin name pin a0 40 ad14 93 pcs3_n/pio19 62 a1 39 ad15 95 pcs5_n/a1/pio3 60 a2 37 ale 7 pcs6_n/a2/pio2 59 a3 36 ardy 8 rd_n 6 a4 35 bhe_n/aden_n 4 res_n 71 a5 34 clkouta 16 rxd/pio28 99 a6 33 clkoutb 17 s0_n /sren_n 11 a7 32 den_n/pio5 49 s1_n /i mdis_n 10 a8 31 drq0/pio12 77 s2_n 9 a9 30 drq1/pio13 76 s6/clk sel1_n /pio29 96 a10 29 dt/r_n/pio4 48 sclk/pio20 3 a11 28 gnd 12 sdata/pio21 100 a12 27 gnd 18 sden0/pio22 2 a13 26 gnd 41 sden1/pio23 1 a14 25 gnd 64 srdy/pio6 46 a15 2 4 gnd 70 tmrin0/pio11 75 a16 23 gnd 89 tmrin1/pio0 72 a17/pio7 22 hlda 44 tmrout0/pio10 74 a18/pio8 20 hold 45 tmrout1/pio1 73 a19/pio9 19 int0 56 txd/pio27 98 ad0 78 int1/select_n 55 ucs_n/once1_n 57 ad1 80 int2/inta0_n/pio31 54 uz i_n/ clksel2_n/ pio26 97 ad2 82 int3/inta1_n/irq 53 v cc 15 ad3 84 int4/pio30 52 v cc 21 ad4 86 lcs_n/once0_n 58 v cc 38 ad5 88 mcs0_n/pio14 50 v cc 61 ad6 91 mcs1_n/pio15 51 v cc 67 ad7 94 mcs2_n/pio24 68 v cc 92 ad8 79 mcs3_n/rfsh_n/pio25 69 whb_n 42 ad9 81 nmi 47 wlb_n 43 ad10 83 pcs0_n/pio16 66 wr_n 5 ad11 85 pcs1_n/pio17 65 x1 13 ad12 87 pcs2_n/pio18 63 x2 14 ad13 90
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 146 1 - 888 - 824 - 4184 2.1.5 ia 188er pqfp package the pinout for the ia 188er pqfp package is as shown in figure 5. the corre sponding pinout is provided in tables 7 and 8. figure 5 . ia 188er pqfp package diagram s d a t a / p i o 2 1 r x d / p i o 2 8 t x d / p i o 2 7 u z i _ n / c l k s e l 2 _ n / p i o 2 6 s 6 / c l k s e l 1 _ n / p i o 2 9 a o 1 5 a d 7 a o 1 4 v c c a d 6 a o 1 3 g n d a d 5 a o 1 2 a d 4 a o 1 1 a d 3 a o 1 0 a d 2 a o 9 i a 1 8 6 e s t q f p a d 1 a o 8 a d 0 d r q 0 / p i o 1 2 d r q 1 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / p i o 1 8 p c s 3 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 s d e n 1 / p i o 2 3 s d e n 0 / p i o 2 2 s c l k / p i o 2 0 r f s h 2 _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n / i m d i s _ n s 0 _ n / s r e n _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 v c c a 1 a 0 g n d g n d w b _ n h l d a h o l d s r d y / p i o 6 n m i d t / r _ n / p i o 4 d e n _ n / p i o 5 m c s 0 _ n / p i o 1 4 i a 1 8 8 e r p q f p
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 146 1 - 888 - 824 - 4184 table 7 . ia 188er p qfp numeric pin listing pin name pin name pin name 1 sden1/pio23 35 a4 68 mcs2_n/pio24 2 sden0/pio22 36 a3 69 mcs3_n/rfsh_n/pio25 3 sclk/pio20 37 a2 70 gnd 4 rfsh2_n/aden_n 38 v cc 71 res_n 5 wr_n 39 a1 72 tmrin1/pio0 6 rd_n 40 a0 73 tmrout1/pio1 7 ale 41 gnd 74 tmrout0/pio10 8 ardy 42 gnd 75 tmrin 0/pio11 9 s2_n 43 wb_n 76 drq1/pio13 10 s1_n /imdis_n 44 hlda 77 drq0/pio12 11 s0_n /sren_n 45 hold 78 ad0 12 gnd 46 srdy/pio6 79 ao8 13 x1 47 nmi 80 ad1 14 x2 48 dt/r_n/pio4 81 ao9 15 v cc 49 den_n/pio5 82 ad2 16 clkouta 50 mcs0_n/pio1 4 83 ao10 17 clkoutb 51 mcs1_n/pio15 84 ad3 18 gnd 52 int4/pio30 85 ao11 19 a19/pio 9 53 int3/inta1_n/irq 86 ad4 20 a18/pio8 54 int2/inta0_n/ pio31 87 ao12 21 v cc 55 int1/select_n 88 ad5 22 a17/pio7 56 int0 89 gnd 23 a16 57 ucs_n/once1_n 90 ao13 24 a15 58 lcs_n/once0_n 91 ad6 25 a14 59 pcs6_n/a2/pio2 92 v cc 26 a13 60 pcs5_n/a1/pio3 93 ao14 27 a12 61 v cc 94 ad7 28 a11 62 pcs3_n/pio19 95 ao15 29 a10 63 pcs2_n/pio18 96 s6/clk sel1 _n/pio29 30 a9 64 gnd 97 uzi_n/ clksel2_n/ pio26 31 a8 65 pcs1_n/pio17 98 txd/pio27 32 a7 66 pcs0_n/pio16 99 rxd/pio28 33 a6 67 v cc 100 sdata/pio21 34 a5
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 146 1 - 888 - 824 - 4184 table 8 . ia 188er p qfp alphabetic pin listing name pin name pin name pin a0 40 ao13 90 pcs3_n/rt s1_n/rtr1_n/pio19 62 a1 39 ao14 93 pcs5_n/a1/pio3 60 a2 37 ao15 95 pcs6_n/a2/pio2 59 a3 36 ardy 8 rd_n 6 a4 35 clkouta 16 res_n 71 a5 34 clkoutb 17 rfsh2_n/aden_n 4 a6 33 den_n/pio5 49 rxd/pio28 99 a7 32 drq0/pio12 77 s0_n /sren_n 1 1 a8 31 drq1/pio13 76 s1_n /imdis_n 10 a9 30 dt/r_n/pio4 48 s2_n 9 a10 29 gnd 12 s6/ c lk sel1_n /pio29 96 a11 28 gnd 18 sclk/pio20 3 a12 27 gnd 41 sdata/pio21 100 a13 26 gnd 42 sden0/pio22 2 a14 25 gnd 64 sden1/pio23 1 a15 24 gnd 70 srdy/pio6 46 a16 23 gnd 89 tmrin0/pio11 75 a17/pio7 22 hlda 44 tmrin1/pio0 72 a18/pio8 20 hold 45 tmrout0/pio10 74 a19/pio9 19 int0 56 tmrout1/pio1 73 ad0 78 int1/select_n 55 txd/pio27 98 ad1 80 int2/inta0_n/ pio31 54 ucs_n/once1_n 57 ad2 82 int3/inta1_n/irq 53 uzi_n/ clksel2_n/ pio26 97 ad3 84 int4/pio30 52 v cc 15 ad4 86 lcs_n/once0_n 58 v cc 21 ad5 88 mcs0_n/pio14 50 v cc 38 ad6 91 mcs1_n/pio15 51 v cc 61 ad7 94 mcs2_n/pio24 68 v cc 67 ale 7 mcs3_n/rfsh_n/pio25 69 v cc 92 ao8 79 nmi 47 wb_n 4 3 ao9 81 pcs0_n/pio16 66 wr_n 5 ao10 83 pcs1_n/pio17 65 x1 13 ao11 85 pcs2_n /pio18 63 x2 14 ao12 87
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 146 1 - 888 - 824 - 4184 2.1.6 pqfp physical dimensions the physical dimensions for the pqfp are as shown in figure 6. figure 6 . pqfp package dimensions legend sy mbol millimeter inch min nom max min nom max a C C 3.40 C C 0.134 a 1 0.25 C C 0.010 C C a 2 2.73 2.85 2.97 0.107 0.112 0.117 b 0.25 0.30 0.38 0.010 0.012 0.015 c 0.13 0.15 0.23 0.005 0.006 0.009 d 23.00 23.20 23.40 0.906 0.913 0.921 d 1 19.9 0 20.00 20.10 0.783 0.787 0.791 e 17.00 17.20 17.40 0.669 0.677 0.685 e 1 13.90 14.00 14.10 0.547 0.551 0.555 e 0.65 bsc . 0.026 bsc . l 0.73 0.88 1.03 0.029 0.035 0.041 l 1 1.60 bsc . 0.063 bsc . y C C 0.10 C C 0.004 0 C 7 0 C 7 notes : 1. dimensions d 1 and e 1 do n ot include mold protrusion , b ut mold mismatch is included. allowable protrusion is 0.25mm/0.010 per side. 2. dimension b does not include dambar protrusion. allowable protrusion is 0.08mm/0.003 total in excess of the b dimension at maximum material condit ion. dambar cannot be located on the lower radius or the foot. 3. controlling dimension: millimeter.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 146 1 - 888 - 824 - 4184 2.2 pin descriptions 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16 C a0 address bus (synchronous outputs with tristate) these pins are the systems source of non - multiplexed i/o o r memory addresses and occur one half clkouta cycle before the multiplexed address/data bus (ad15 C ad0 for the ia186er or ao15 C ao8 and ad7 C ad0 for the ia188er). the address bus is tristated during a bus hold or reset. 2.2.2 ad15 C ad8 ( ia 186er ) address /data bus (l evel - sensitive synchronous inouts with tristate) these pins are the systems source of time - multiplexed i/o or memory addresses and data. the address function of these pins can be disabled ( see bhe_n/aden_n pin description ) . if the address function of these pins is enabled, the address will be present on this bus during t 1 of the bus cycle and data will be present during t 2 , t 3 , and t 4 of the same bus cycle. if whb_n is not active, these pins are tristated during t 2 , t 3 , a nd t 4 of the bus cycle. the address/data bus is tristated during a bus hold or reset. these pins can be used to load the internal reset configuration register (rescon, offset 0f6h) with configuration data during a power - on reset (por). 2.2.3 ad7 C ad0 address/data bus (level - sensitive synchronous inouts with tristate) these pins are the systems source of time - multiplexed low - order byte of the addresses for i/o or memory and 8 - bit data. the low - order address byte will be present on this bus during t 1 of the bus cy cle and the 8 - bit data will be present during t 2 , t 3 , and t 4 of the same bus cycle. the address function of these pins can be disabled (see bhe_n/aden_n pin description ). if wlb_n (ia186er) is not active, these pins are tris tated during t 2 , t 3 , and t 4 of the bus cycle. the address/data bus is tristated during a bus hold or reset. 2.2.4 ao15 C ao8 ( ia 188er ) address - only bus (level - sensitive synchronous outputs with tristate) the address - only bus will contain valid high - order address bits during the bus cycle (t 1 , t 2 , t 3 , and t 4 ) if the bus is enabled. these pins are combined with ad7 C ad0 to complete the multiplexed address bus and are tristated during a bus hold or reset condition.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 31 of 146 1 - 888 - 824 - 4184 2.2.5 ale address latch enable (synchronous output) this signal indicates the presence of an address on the address /data bus ( ad15 C ad0 for the ia186er or ao15 C ao8 and ad7 C ad0 for the ia188er), which is guaranteed to be valid on the falling edge of ale . 2.2.6 ardy asynchronous ready (level - sensitive asynchronous input) this asynchronous signal provides an indication to the microcontroller that the addressed i/o device or memory space will complete a data transfer. this active high signal is asynchronous with respect to clkouta and if the falling edge of ardy is not syn chronized to clkouta , an additional clock cycle may be added signal ardy should be tied high to maintain a permanent assertion of the ready condition. on the other hand, if the ardy signal is not used by the system it should be tied low, which passes cont rol to the srdy signal. 2.2.7 bhe_n/aden_n ( ia 186er) bus high enable (synchronous output with tristate)/address enable (input with internal pull - up) the bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower, or both) are inv olved in the current memory access bus cycle as shown table 9. table 9 . bus cycle types for bhe_n and ad0 bhe_n ad0 type of bus cycle 0 0 word transfer 0 1 high - byte transfer (bits [15 C 8 ] ) 1 0 low - byte transfer (bits [7 C 0 ] ) 1 1 refresh the bhe_n does not require latching and during bus hold and reset is tristated. it is asserted during t 1 and remains so through t 3 and t w . the high - and low - byte write enable functions of bhe_n and ad0 are performed by whb_n and wlb_n , respe ctively. when using the ad bus, dram refresh cycles are indicated by bhe_n/aden_n and ad0 both being high. during refresh cycles the a and ad bus es may not have the same address during the address phase of the ad bus cycle necessitating the use of ad0 as a determinant for the refresh cycle rather than a0. an additional signal is used for pseudo - static ram (psram) refreshes (see mcs3_n/rfsh_n pin description). there is a weak internal pull - up on bhe_n/aden_n obviating the need for an external pull - up and re ducing power consumption.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 146 1 - 888 - 824 - 4184 holding aden_n high or letting it float during por passes control of the address function of the ad bus ( ad15 C ad0 ) during lcs and ucs bus cycles from aden_n to the disable address (da) bit in low - memory chip select (lmcs) and uppe r memory chip select (umcs) registers. when the address function is selected, the memory address is placed on the a19 C a0 pins. holding aden_n low during por, both the address and data are driven onto the ad bus independently of the da bit setting. this pin is normally sampled one clock cycle after the rising edge of res_n . 2.2.8 clkouta clock output a (synchronous output) this pin is the internal clock output to the system. bits [9 C 8] and bits [2 C 0] of the power - save control register (pdcon) control the ou tput of this pin, which may be tristated, output the internal processor frequency (divide by two, x1 or x4), or output the power save frequency (internal processor frequency after divisor). the clkouta can be used as a full - speed clock source in power - sav e mode. the ac timing specifications that are clock - related refer to clkouta , which remains active during reset and hold conditions. 2.2.9 clkoutb clock output b (synchronous output) this pin is an additional clock output to the system . bits [11 C 10] and [2 C 0] of the power - save control register (pdcon) control the output of this pin, which may be tristated, internal processor frequency (divide by two, x1 or x4), or may output the power - save frequency (internal processor frequency after divisor). the clkoutb rem ains active during reset and hold conditions. 2.2.10 den_n/pio5 data enable strobe (synchronous output with tristate) this pin provides an output enable to an external bus data bus transmitter or receiver. this signal is asserted during i/o, memory, and interrup t acknowledge processes and is deasserted when dt/r_n undergoes a change of state. it is tristated for a bus hold or reset. 2.2.11 drq1/pio13 C drq0/pio12 dma requests (synchronous level - sensitive inputs) an external device that is ready for dma channel 1 or 0 t o carry out a transfer indicates to the microcontroller this readiness on these pins. they are level triggered, internally synchronized, not latched, and must remain asserted until handled . 2.2.12 dt/r_n/pio4 data transmit or receive (synchronous output with tri state) the microcontroller transmits data when dt/r_n is set high and receives data when this pin is asserted low. it floats during a reset or bus hold condition. 2.2.13 gnd ground six or seven pins, depending on package, connect the microcontroller to the syst em ground.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 146 1 - 888 - 824 - 4184 2.2.14 hlda bus hold acknowledge (synchronous output) this pin is set high to signal the system that the microcontroller has ceded control of the local bus, in response to a high on the hold signal by an external bus master, after the microcontroller h as completed the current bus cycle. the assertion of hlda is accompanied by the tristating of den_n, rd_n, wr_n, s2_n C s0_n, ad15 C ad0, s6, a19 C a0, bhe_n, whb_n, wlb_n, and dt/r_n , followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n C mcs0_n , pcs6_n C pcs5_n, and pcs3_n C pcs0_n . the external bus master releases control of the local bus by the deassertion of hold that in turn induces the microcontroller to deassert the hlda . the microcontroller can take control of the bus if necessary (to execu te a refresh for example), by deasserting hlda without the bus master first deasserting hold . this requires that the external bus master be able to deassert hold to permit the microcontroller to access the bus. 2.2.15 hold bus hold request (synchronous level - sen sitive input) this pin is set high to signal the microcontroller that the system requires control of the local bus. the hold latency time (time between the hold and hlda ) depends on the current processor activity when the hold is received. a hold request is second only to a dram or psram refresh request in priority of processor activity requests. if a hold request is received at the moment a dma transfer starts, the hold latency can be up to 4 bus cycles. (this happens only on the ia186er when a word tr ansfer is taking place from an odd to an odd address.) this means that the latency may be 16 clock cycles without wait states. furthermore, if lock transfers are being performed, then the latency is increased during the locked transfer. 2.2.16 int0 maskable int errupt request 0 (asynchronous input) the int0 pin provides an indication that an interrupt request has occurred, and provided that int0 is not masked, program execution will continue at the location specified by the int0 vector in the interrupt vector tab le. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. 2.2.17 int1/select_n maskab le interrupt request 1/slave select (both are asynchronous inputs) the int1 pin provides an indication that an interrupt request has occurred, and provided that int1 is not masked, program execution will continue at the location specified by the int1 vecto r in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized, the assertion of the interrupt request must be maintained until it is h andled. the select_n pin provides an indication to the microcontroller that an interrupt type has been placed on the address/data bus when the internal interrupt control unit is slaved to an external
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 146 1 - 888 - 824 - 4184 interrupt controller. before this can occur, however, the int0 pin must have already indicated an interrupt request. 2.2.18 int2/inta0_n/pio31 maskable interrupt request 2 (asynchronous input)/interrupt acknowledge 0 (synchronous output) the int2 pin provides an indication that an interrupt request has occurred, an d provided that int2 is not masked, program execution will continue at the location specified by the int2 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - trigg ered. to ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. when int0 is configured for cascade mode, int2 changes its function to inta0_n . the inta0_n function indicates to the system that the mi crocontroller requires an interrupt type in response to the interrupt request int0 when the microcontrollers interrupt control unit is in cascade mode. the peripheral device that issued the interrupt must provide the interrupt type. 2.2.19 i nt3/inta1_n/irq mask able interrupt request 3 (asynchronous input)/interrupt acknowledge 1 (synchronous output)/ i nterrupt request (synchronous output) the int3 pin provides an indication that an interrupt request has occurred. if int3 is not masked, program execution will con tinue at the location specified by the int3 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized, the assertion of the i nterrupt request must be maintained until it is handled. when int1 is configured to be in cascade mode, int3 changes its function to inta1_n . the inta1_n function indicates to the system that the microcontroller requires an interrupt type in response to t he interrupt request int1 when the microcontrollers interrupt control unit is in cascade mode. the peripheral device that issued the interrupt must provide the interrupt type. i rq allows the microcontroller to output an interrupt request to the external master interrupt controller when the interrupt control unit of the microcontroller is in slave mode. 2.2.20 int4/pio30 maskable interrupt request 4 (asynchronous input) the int4 pin provides an indication that an interrupt request has occurred, and provided that int4 is not masked, program execution will continue at the location specified by the int4 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensur e that it is recognized, the assertion of the interrupt request must be maintained until it is handled.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 146 1 - 888 - 824 - 4184 2.2.21 lcs_n/once0_n lower memory chip select (synchronous output with internal pull - up)/once mode request (input) the lcs_n pin provides an indication that a memory access is occurring to the lower memory block. the size of the lower memory block and its base address are programmable, with the size adjustable up to 512 kbytes. the lcs_n pin is held high during bus hold. the once0_n pin (once C on c ircuit e m ulation) and its companion pin, once1_n, define the microcontroller mode during reset. these two pins are sampled on the rising edge of res_n and if both are asserted low the microcontroller starts in once mode, else it starts normally. in once mode, all pins are tristated and remain so until a subsequent reset. to prevent the microcontroller from entering once mode inadvertently, this pin has a weak pull - up that is only present during reset. this pin is not tristated during bus hold. 2.2.22 mcs2_n mcs0_n (pio 24, pio15, pio 14) midrange memory chip selects (synchronous outputs with internal pull - up) the mcs2_n and mcs0_n pins provide an indication that a memory access is in progress to the first, second or third midrange memory block. the size of the midrange memory block s and its base address es are programmable. the mcs2_n C mcs0_n are held high during bus hold and have weak pull - ups that are only present during reset. 2.2.23 mcs3_n/rfsh_n / pio25 midrange memory chip select (synchronous output with internal pull - up)/ automatic refresh (synchronous output) the mcs3_n pin provides an indication that a memory access is in progress to the fourth region of the midrange memory block. the size of the midrange memory block and its base address are programmable. the mcs3_n is held high during bus hold and has a weak pull - up that is present only during reset. the rfsh_n signal is timed for auto refresh to psram or dram devices. the refresh pulse is output only when the psram or dram mode bit is set (edram register bit [15]). this pulse is of 1.5 clock - pulse duration with the rest of the refresh cycle made up of a deassertion period such that the overall refresh time is met. this pin is not tristated during a bus hold. 2.2.24 nmi nonmaskable interrupt (synchronous edge - sensitive in put) unlike int4 C int0 , this is the highest priority interrupt signal and cannot be masked. upon the assertion of this interrupt (transition from low to high), program execution is transferred to the nonmaskable interrupt vector in the interrupt vector t able and this interrupt is initiated at the next instruction boundary. for recognition to be assured, the nmi pin must be held high for at least a clkouta period so that the transition from low to high is latched and synchronized internally. the interrup t will begin at the next instruction boundary.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 146 1 - 888 - 824 - 4184 the nmi is not involved in the priority resolution process that deals with the maskable interrupts and does not have an associated interrupt flag. this allows for a new nmi request to interrupt an nmi servi ce routine that is already underway. when an interrupt is taken by the processor the interrupt flag if is cleared, disabling the maskable interrupts. if the maskable interrupts are reenabled during the nmi service routine (e.g., by use of sti instruction ), the priority resolution of maskable interrupts will be unaffected by the servicing of the non - maskable interrupt (nmi). note: for this reason, it is strongly recommended that the nmi interrupt service routine does not enable the maskable interrupts. 2.2.25 pc s3_n C pcs0_n (pio19 C pio16) peripheral chip selects 3 C 0 (synchronous outputs) the pcs3_n C pcs0_n pins provide an indication that a memory access is underway for the corresponding region of the peripheral memory block (i/o or memory address space). the base a ddress of the peripheral memory block is programmable. the pins are held high during both bus hold and reset. these outputs are asserted with the ad address bus over a 256 - byte range each. 2.2.26 pcs5_n/a1 / pio3 peripheral chip select 5 (synchronous output)/latc hed address bit 1 (synchronous output) the pcs5_n signal provides an indication that a memory access is underway for the sixth region of the peripheral memory block (i/o or memory address space). the base address of the peripheral memory block is programm able. the pcs5_n is held high during both bus hold and reset. this output is asserted with the ad address bus over a 256 - byte range. this a1 pin provides an internally latched address bit 1 to the system when the ex bit (bit [7]) in the mcs_n and pcs_n a uxiliary (mpcs) register is 0. it retains its previously latched value during a bus hold. 2.2.27 pcs6_n/a2 / pio2 peripheral chip select 6 (synchronous output)/latched address bit 2 (synchronous output) the pcs6_n signal provides an indication that a memory access is underway for the seventh region of the peripheral memory block (i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs6_n is held high during both bus hold and reset. this output is asserted with the a d address bus over a 256 - byte range. the a2 pin provides an internally latched address b it [2] to the system when the ex bit (bit [7]) in the mcs_n and pcs_n auxiliary (mpcs) register is 0. it retains its previously latched value during a bus hold.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 146 1 - 888 - 824 - 4184 2.2.28 pio31 C pio0 programmable i/o pins ( asynchronous input/output open - drain) there are 32 individually programmable i/o pins provided (see table 15, default status of pio pins at reset ). 2.2.29 rd_n read strobe (synchronous output with tristate) the rd_n pin provides an indication to the system that a memory or i/o read cycle is underway. it will not be asserted before the ad bus is floated during the address to data transition. the rd_n pin is tristated during bus hold. 2.2.30 r es_n reset (asynchronous level - sensitive input) the res_n pin forces a reset o f the microcontroller. its schmitt trigger allows por generation via an rc network. when this signal is asserted, the microcontroller immediately terminates its present activit y, clears its internal logic, and transfers cpu control to the reset address, ffff0h. the res_n must be asserted for at least 1 ms. because it is synchronized internally it may be asserted asynchronously to clkouta . furthermore, v cc must be within spec ification and clkouta must be stable for more than four of its clock periods for the period that res_n is asserted. the microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of res_n . 2.2.31 rfsh2_n/aden_n ( ia 188er) refresh 2 (synchronous output with tristate)/address enable (input with internal pull - up) the rfsh2_n indicates that a dram refresh cycle is being performed when it is asserted low. however, this is not valid in psram mode where mcs3_n/rfsh_n is used instead. if the aden_n pin is held high during por, the ad bus ( ao15 C ao8 and ad7 C ad0 for the ia188er) is controlled during the address portion of the lcs and ucs bus cycles by the da bit (bit [7]) in the lcs and ucs registers. if the da bit is 1, the address is acce ssed on the a19 C a0 pins, reducing power consumption. the weak pull - up on this pin obviates the necessity of an external pull - up. if the aden_n pin is held low during por, the ad bus is used for both addresses and data without regard for the setting of th e da bits. the rfsh2_n/aden_n is sampled one crystal clock cycle after the rising edge of res_n and is tristated during bus holds and once mode. 2.2.32 rxd/pio28 receive data (asynchronous input) this signal connects asynchronous serial receive data from the sy stem to the asynchronous serial port.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 146 1 - 888 - 824 - 4184 2.2.33 s0 _n, s1_n (imdis_n), s 0 _n (sren_n) bus cycle status (synchronous outputs with tristate) these three signals inform the system of the type of bus cycle in progress. the s2_n may be used to indicate whether the curre nt access is to memory or i/o, and s1_n may be used to indicate whether data is being transmitted or received. these signals are tristated during bus hold and hold acknowledge. the coding for these pins is presented in t able 10 . imdis_n: internal memory disable (input, pullup); if low during reset, internal memory is disabled. sren_n: show read enable (input, pullup); if low during reset, reads from internal memory are driven on the external address/data bus. table 10 . bus cycle types for s2_n, s1_n, and s0_n s2_n s1_n s0_n bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive) 2.2.34 s6 /clksel1_n/pio29 bus cycle status bit 6 (synchronous output)/clock divide by 2 (input with internal pull - up) the s6 signal is high during the second and remaining cycle periods (i.e., t 2 C t 4) , indicating that a dma - initiated bus cycle is underway. the s6 is tristated during bus hold or reset. combined with uzi_n/clksel2_n to select clock mode. if low, input clock is divided by two and the pll is disabled. default, because of pull - ups, is for x4 clock mode. this pin is sampled on the rise of reset. note: if this pin is used as pio29 and configured as an input, care should be taken that it is not driven low during por. because this pin has an internal pull - up, it is not necessary to drive the pin high even though it defaults to an input pio.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 146 1 - 888 - 824 - 4184 2.2.35 s clk / pio20 se rial clock (synchronous outputs with tristate) because this pin provides a slave device with a synchronous serial clock it permits synchronization of the transmit and receive data exchanges between the slave and the microcontroller. the sclk is the result of dividing the internal clock by 2, 4, 8, or 16, depending on the contents of the synchronous serial control (ssc) register bits [5 C 4]. accessing either the ssr or ssd registers activates the sclk for eight cycles. when sclk is not active, the microcon troller holds it high. 2.2.36 sdata/ pio2 1 serial data (synchronous inout) the sdata pin connects a slave device to synchronous serial transmit and receive data. the last value is retained on this pin when it is inactive. 2.2.37 sden1/pio23 C sden0/pio22 serial data enables (synchronous outputs with tristate) the sden1 C sden0 pins facilitate the transfer of data on ports 1 and 0 of the synchronous serial interface (ssi). either sden1 or sden0 is asserted by the microcontroller at the start of the data transfer and is de - asserted when the transfer is completed. these pins are held low by the microcontroller when they are inactive. 2.2.38 srdy/pio6 synchronous ready (synchronous level - sensitive input) this signal is an active high input synchronized to clkouta and indicates to the microcontroller that a data transfer will be completed by the addressed memory space or i/o device. in contrast to the asynchronous ready ( ardy ), which requires internal synchronization, srdy permits easier system timing because it already synchroniz ed. tying srdy high will always assert this ready condition. tying it low will give control to ardy . 2.2.39 tmrin0/pio11 timer input 0 (synchronous edge - sensitive input) this signal may be either a clock or control signal for the internal timer 0. the timer i s incremented by the microcontroller after it synchronizes a rising edge of tmrin0 . when not used, tmrin0 must be tied high, or when used as pio11 , it is pulled up internally. 2.2.40 tmrin1/pio0 timer input 1 (synchronous edge - sensitive input) this signal may be either a clock or control signal for the internal timer 1. the timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin1 . when not used, tmrin1 must be tied high, or when used as pio0 , it is pulled up internally.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 146 1 - 888 - 824 - 4184 2.2.41 tmrout0/ pio10 timer output 0 (synchronous output) this signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. it is tristated during a bus hold or reset. 2.2.42 tmrout1/pio1 timer output 1 (synchronous output) this signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. it is tristated during a bus hold or reset. 2.2.43 txd/pio27 transmit data (asynchronous output) this pin provides the system with asynchronous serial transmit data from the serial port. 2.2.44 ucs_n/once1_n upper memory chip select (synchronous output)/once mode request 1 (input with internal pull - up) the ucs_n pin provides an indication that a memory access is in progress to the upper memory block. the size of the upper memory block and its base address are programmable, with the size adjustable up to 512 kbytes. the ucs_n pin is held high during bus hold. after power - on - reset , ucs_n is asserted low and program execution begins at ffff0h. its default configuration is a 64 - kbyte memory range from f0000h to fffffh. the once0_n pin (once C on c ircuit e mulation) and its companion pin, once1_n, define the microcontroller mode during reset. these two pins are sampled on the rising edge of res_n and if both are asserted low th e microcontroller starts in once mode, else it starts normally. in once mode, all pins are tristated and remain so until a subsequent reset. to prevent the microcontroller from entering once mode inadvertently, this pin has a weak pull - up that is only pr esent during reset. this pin is not tristated during bus hold. 2.2.45 uzi_n/clksel2_n/pio26 upper zero indicate (synchronous output)/clock select 2 (input, pullup) this pin allows the designer to determine if an access to the interrupt vector table is in progres s by oring it with bits [15 C 10] of the address and data bus ( ad15 C ad10 on the ia186er and ao15 C ao10 on the ia188er). the uzi_n is the logical or of the inverted a19 C a16 bits. it asserts in the first period of a bus cycle and is held throughout the cycle. clksel2_n is combined with s6/clksel1_n/pio29 to select clock mode. if low, part enters clock mode x1. default, because of pull - ups, is for x4 clock mode. this is sampled on the rise of reset. 2.2.46 v cc power supply (input) these pins supply power (+3.3v + 10%) to the microcontroller.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 146 1 - 888 - 824 - 4184 2.2.47 whb_n ( ia 186er ) write high byte (synchronous output with tristate) the whb_n and wlb_n pins indicate to the system which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. the whb_n is asserted with ad1 5 C ad8 and is the logical or of bhe_n and wr_n . it is tristated during reset. 2.2.48 wlb_n/wb_n write low byte ( ia 186er ) (synchronous output with tristate)/write byte ( ia 188er ) (synchronous output with tristate) the wlb_n and whb_n pins indicate to the system whi ch bytes of the data bus (upper, lower, or both) are taking part in a write cycle. the wlb_n is asserted with ad7 C ad0 and is the logical or of ad0 and wr_n . it is tristated during reset. on the ia188er microcontroller, wb_n provides an indication that a write to the bus is occurring. it shares the same early timing as that of the non - multiplexed address bus, and is associated with ad7 C ad0 . it is tristated during reset. 2.2.49 wr_n write strobe (synchronous output) the wr_n pin indicates to the system that the data currently on the bus is to be written to a memory or i/o device. it is tristated during a bus hold or reset. 2.2.50 x1 crystal input (input) the x1 and x2 pins are the connections for a fundamental - mode, parallel - resonant crystal used by the internal oscil lator circuit. an external clock source for the microcontroller is connected to x1 . the x2 pin is left unconnected. 2.2.51 x2 crystal input (input) the x1 and x2 pins are the connections for a fundamental - mode, parallel - resonant crystal used by the internal os cillator circuit. an external clock source for the microcontroller is connected to x1 . the x2 pin is left unconnected. 2.3 pins used by emulators the following pins are used by emulators: a19 C a0 ao15 C ao8 ( on the ia 188er ) ad7 C ad0 ale bhe_n/aden_n (on the ia 186er ) clkouta rfsh2_n/aden_n (on the ia188er )
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 146 1 - 888 - 824 - 4184 rd_n s2_n C s0_n s6/ clksel1_n uzi_n /clksel2_n emulators require that s6/ clksel1_n and uzi_n /clksel2_n be configured as their normal functions (i.e., as s6 and uzi_n , respectively). holding bhe_n/aden_n (ia186e r) or rfsh_n/aden_n (ia188er) low during the rising edge of res_n, will cause s6 and uzi_n to be configured in their normal functions at reset instead of pios.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 146 1 - 888 - 824 - 4184 3. maximum ratings, thermal characteristics, and dc parameters t he absolute maximum ratings, the rmal characteristics, and dc parameters are provided in tables 11 through 1 3 , respectively. table 11 . ia 186er and ia 188er absolute maximum ratings parameter rating storage temperature ? 40 c to +1 50 c voltage on any pin with resp ect to v ss ?0. 3 v to +(v cc + 0. 3 ) v table 12 . ia 186er and ia 188er thermal characteristics symbol characteristic value t a ambient temperature - 40 c to 85 c table 13 . dc characteristics over industrial operating ranges symbol parameter description test conditions min max unit v cc supply voltage (@ 3.3 v operation) C 3.0 3.6 v v il input low voltage C ? 0.8 v v il1 clock input low voltage C ? 0.8 v v ih input high voltage C 2.0 v cc + 2.2 v v ol output low voltages i ol = 2 - 2.4 ma C 0.4 0 v v oh output high voltages i oh = ? 2.4 ma @ 2.4 v 2.4 v cc + 0.5 v i cc power supply current @ 0 c v cc = 3.3 v C 5.9 ma/ mhz i li input leakage current C C 10 a i lo output leakage current C C 10 a
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 146 1 - 888 - 824 - 4184 4. device architectur e a functional block diagram of the ia 186er /ia 188er is shown in figure 7 . this microcontroller consists of the following functional blocks. bus interface and control (bic) 32 kbytes ram peripheral control and registers chip selects and control (csc) pro grammable i/o clock and power management dma interrupt controller timers asynchronous serial port synchronous serial interface watchdog timer instruction decode and execution 4.1 bus interface and control bic manages all accesses to external memory , external p eripherals and the internal 32 kbyte ram . these peripherals may be mapped either in memory space or i/o space. the bic supports both multiplexed and non - multiplexed bus operations. multiplexed address and data are provided on the ad 15 C ad 0 bus, while a n on - multiplexed address is provided on the a 19 C a 0 bus. the a bus provides address information for the entire bus cycle (t 1 C t 4 ), while the ad bus provides address information only during the first phase of the bus cycle (t 1 ) . for more details regarding bus cycles, see the ac waveforms at the end of this datasheet. the ia 186er microcontroller provides two signals t hat serve as byte write enables, write high byte ( whb_n ) and write low byte ( wlb_n ). t he ia 188er microcontroller requires only a single write byt e ( wb_n ) signal to support its 8 - bit data bus. the whb_n is the logical or of the bhe_n and wr_n . the wlb_n is the logical or of ad0 and wr_n . the wb_n is low whenever a byte is written to the ia 188er data bus ad 7 C ad 0. the byte write enables are driven in conjunction with the non - multiplexed address bus a 19 C a 0 to support the timing requirements of common srams. the bic also provides support for psram devices. psram is supported in only the lower chip select ( lcs_n ) area. in order to support psram, the csc must be appropriately programmed (s ee section 4.7, chip selects ) .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 146 1 - 888 - 824 - 4184 figure 7 . functional block diagram ( ) u z i _ n / c l k s e l 2 _ n s 6 / c l k s e l 1 _ n h o l d h l d a s r d y d e n _ n a r d y d t / r _ n s 2 _ n p e r i p h e r a l c o n t r o l a n d r e g i s t e r s c h i p s e l e c t s a n d c o n t r o l p r o g r a m m a b l e i / o r d _ n w h b _ n w l b _ n w r _ n a l e d e n _ n a [ 1 9 : 0 ] a d [ 1 5 : 0 ] l c s _ n / o n c e 0 _ n m c s 3 _ n / r f s h _ n u c s _ n / o n c e 1 _ n p c s 5 _ n / a 1 p c s 6 _ n / a 2 p c s 3 _ n C p c s 0 _ n m c s 2 _ n C m c s 0 _ n p i o [ 3 1 : 0 ] c l o c k a n d p o w e r m a n a g e m e n t d i r e c t m e m o r y a c c e s s i n t e r r u p t c o n t r o l l e r t i m e r s a s y n c h r o n o u s s e r i a l p o r t s y n c h r o n o u s s e r i a l p o r t i n s t r u c t i o n d e c o d e a n d e x e c u t i o n d r q 0 d r q 1 c l k o u t a c l k o u t b v c c g n d i n t 4 i n t 3 / i n t a 1 _ n / i r q i n t 2 / i n t a 0 _ n i n t 1 / s e l e c t _ n i n t 0 n m i t m r i n 0 t m r o u t 0 t m r i n 1 t m r o u t 1 t x d 0 r x d 0 s c l k s d e n 0 s d e n 1 s d a t a 3 2 k b y t e s r a m w a t c h d o g t i m e r s 1 _ n / i m d i s _ n s 0 _ n / s r e n _ n r e s _ n b u s i n t e r f a c e a n d c o n t r o l
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 146 1 - 888 - 824 - 4184 4.2 clock and power management a phase - lock - loop (pll) and a second programmable system clock output ( clkoutb ) are included in the clock and power management unit. see figure 8. figure 8 . crystal configuration 4.3 system clocks if required, the internal oscillator can be driven by an external clock source that should be connected to x1, leaving x2 unconnected. the clock outputs clkouta and clkoutb may be enabled or disabled individually (power - save control register (pdcon) bits [ 11 C 8 ] ). these clock control bits allow one clock output to run at the internal system frequency and the other to run at the power - save frequency (see figure 9) . figure 9 . organization of clock c r y s t a l x 1 i a 1 8 6 e r / i a 1 8 8 e r x 2 c 2 c 1 r e c o m m e n d e d r a n g e o f v a l u e s f o r c 1 a n d c 2 a r e : c 1 = 1 5 p f 2 0 % c 2 = 2 2 p f 2 0 %
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 146 1 - 888 - 824 - 4184 4.4 power - save mode the cpu and peripherals operate at a slower clock frequency when in power save mode , reducing power consumption and thermal dissipation. should an interrupt occur, the microcontroller returns to its normal operating frequency automatically on the internal clocks next rising edge in t 3 . any clock - dependent devic es should be reprogrammed for the change in frequency during the power - save mode period. 4.5 initialization and reset r es_n (reset) must be held low for 1 ms during power - up to initialize the microcontroller correctly. this operation makes the device cease al l instruction execution and local bus activity. the microcontroller begins instruction execution at physical address ffff0h when res_n becomes inactive and after an internal processing interval with ucs_n is asserted and three wait states. reset also set s up certain registers to predetermined values and resets the watchdog timer. 4.6 reset configuration register the data on the address/data bus ( ad15 C ad0 for the ia 186er , ao15 C ao8 and ad7 C ad0 for the ia 188er ) are written into the reset configuration register w hen reset is low. this data is held in the reset configuration register after reset is de - asserted. this configuration data may be placed on the address/data bus by using weak external pull - up and pull - down resistors or applied to the bus by an external driver, as the processor does not drive the bus during reset. it is a method of supplying the software with some initial data after a reset; for example, option jumper positions. 4.7 chip selects chip - select generation is programmable for memories and periphe rals. programming is also available to produce ready - and wait - state generation plus latched address bits a1 and a2 . for all memory and i/o cycles, the chip - select lines are active within their programmed areas, regardless of whether they are generated b y the internal dma unit or the cpu. there are six chip - select outputs for memories and a further six for peripherals whether in memory or i/o space. the memory chip - selects are able to address three memory ranges, whereas the peripheral chip - selects are u sed to address 256 - byte blocks that are offset from a programmable base address. writing to a chip - select register enables the related logic even if the pin in question has another function (e.g., if the pin is programmed to be a pio ) . in addition, there is a chip - select for the internal memory. 4.8 chip - select timing for normal timing, the ucs_n and lcs_n outputs are asserted with the non - multiplexed address bus. the other chip selects assert with the multiplexed address/databus.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 146 1 - 888 - 824 - 4184 4.9 ready - and wait - state progr amming each of the memory or peripheral chip - select lines can require a ready signal that can be the ardy or srdy signal. the chip - select control registers (umcs, lmcs, mmcs, pacs, and mpcs) each have a single bit that selects whether the external ready s ignal is to be used or not ( r2 , bit [ 2 ] ). r1 and r0 ( bits [ 1 C 0 ] ) in these regis ters control the number of wait states that are inserted during each access to a memory or peripheral location (from 0 to 3). the control registers for pcs3_n C pcs0_n us e three bits, r3, r1 C r0 ( bits [ 3 ] , [ 1 C 0 ] ) to provide 5, 7, 9, and 15 wait - states in addition to the original values of 0 to 3 wait states. in the case where an external ready has been selected as required, internally programmed wait - states will always be complete d before the external ready can finish or extend a bus cycle. as an example, consider a system in which the number of wait states to be inserted has been set to 3 . the external ready pin is sampled by the processor during the first wait cycle. the acces s is completed after 7 cycles (4 cycles plus 3 wait cycles) if the ready is asserted. alternatively, if the ready is not asserted during the first wait cycle , the access is prolonged until ready is asserted and two more wait states are inserted followed b y t 4 . 4.10 chip select overlap overlapping chip selects are configurati ons where more than one chip select is asserted for the same physical address. for example, if pcs is configured in i/o space with lcs or any other chip select configured for memory, addres s 00000h is not overlapping the chip selects. note: it is not recommended that multiple chip - select signals be asserted for the same physical address, although it may be inescapable in certain systems. if this is the case, then all overlapping chip - sel ects must have the same external ready configurat ion and the same number of wait states to be inserted into access cycles. internal signals are employed to access the peripheral control block (pcb) and these signals serve as chip selects t hat are configure d with no wait states and no external ready. therefore, the pcb can be programmed with addre sses that overlap external chip selects only if these chip selects are configured in the same manner. note: caution is advised in the use of the da bit in the lmc s or umcs registers when overlapping an additional chip select with either the lcs_n or ucs_n . setting the da bit to 1 prevents the address from being driven onto the ad bus for all accesse s for which the respective chip select is active, including those for which multiple selects are active. the mcs_n and pcs_n pins are du al - purpose pins, either as chip selects or pio inputs or outputs. however, the respective ready - and wait - state configurations for their chip - select function will be in effect regardles s of the function for which these pins are programmed. this requires that
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 146 1 - 888 - 824 - 4184 even if these pins are configured as pio and enabled (by writing to the mmcs and mpcs registers for the mcs_n chip selects and to the pacs and mpcs registers for the pcs_n chip sele cts), the ready - a nd wait - state settings for them must agree with those for any overlapping chip selects as though t hey were configured as chip selects. al though pcs4_n is not available as an external pin , it has ready - and wait - state logic and must follow the rules for overlapping chip - selects. conversely, pins pcs6_n and pcs5_n have ready - and wait - state logic that is disabled when configured as address bits a2 and a1 , respectively. note: if chip - select configuration rules are not followed, the processo r may hang with the appearance of waiting for a ready signal even in a system where ready ( ardy or srdy ) is always set to 1. 4.11 upper memory chip select the ucs_n chip select is for the top of memory. on reset, the micro controller begins fetching and executi ng instructions at memory location ffff0h. as a result, upper memory is usually us ed for instruction memory. to this end, ucs_n is active on reset and has a memory range of 64 kbytes (f0000h to fffffh) by default , along with external ready required and 3 wait states automatically inserted. the lower boundary of ucs_n is programmable to provide ranges of 64 to 512 kbytes. 4.12 low memory chip select the lcs_n chip - select is for lower memory. as the interrupt vector table is at the bottom of memory beginning a t 00000h, this pin us usually us ed for control data memory. unlike ucs_n , this pin is inactive on reset, but can be activated by any read or write to the lmcs register. 4.13 midrange memory chip selects there are four midrange chip selects, mcs3_n C mcs0_n , whic h may be used in a user - located memory block. with some exceptions, the base address of the memory block may be located anywhere in the 1 - mbyte memory address space (those used by the ucs_n and lcs_n chip selects , as well as the pcs6_n, pcs5_n, and pcs3_n C pcs0_n , are excluded) . if the pcs_n chip selects are mapped to i/o space , then the mcs address range can overlap the pcs address range. both the midrange memory chip select (mmcs) register and the mcs and pcs auxiliary (mpcs) registers are used to progra m the four midrange chip selects. the mpcs register is used to configure the block size, whereas the mmcs register configures the base address, the ready condition, and the wait states of the memory block accessed by the mcs_n pin. the chip selects ( mcs3 _n C mcs0_n) are activated by performing a write operation of the mmcs and mpcs registers. the assertion of the mcs outputs occurs with the same timing as the multiplexed ad address bus ( ad15 C ad0 on the ia 186er or ao15 C ao8 and ad7 C ad0 on the ia 188er ). the a19 C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 146 1 - 888 - 824 - 4184 a0 may be used for address selection, but the timing will be delayed by a half clock cycle over the timing used for the ucs_n and lcs_n. 4.14 peripheral chip selects there are six peripheral chip selects ( pcs6_n, pcs5_n, and pcs3_n C pcs0_n ) that may be used within a user - defined memory or i/o block. the base address of this user - defined memory block can be located anywhere within the 1 - mbyte memory address space except for the spaces associated with the ucs_n , lcs_n , and mcs_n chip selects. or it may be pr ogrammed to the 64 kbyte i/o space. the pcs4_n pin is not available. both the peripheral chip select (pacs) register and the mcs and pcs auxiliary register (mpcs) registers are used to program the six peripheral chip selects pcs6_n, pcs5_n, and pcs3_n C pcs 0_n. the pacs register sets the base address, the ready condition, and the wait states for the pcs3_n C pcs0_n outputs. the mpcs register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1 and a2 , respectively. when these pins are chip selects , the mpcs register also configures them as being active during m emory or i/o bus cycles and their ready condition and wait states. none of the pcs_n pins are active at reset. both the peripheral chip select (pacs) register and the mcs and pcs auxiliary register (mpcs) registers must be read or written to activate the pcs_n pin s a s chip selects. the pcs6_n and pcs5_n may be programmed to have 0 to 3 wait states, whereas pcs3_n C pcs0_n may be programmed to have these and 5, 7, 9, or 15 wait state s. 4.15 refresh control the refresh control unit (rcu) generates refresh bus cycles. the rcu generates a memory read request after a programmable period of time to the bus interface unit. the ena bit in the enable rcu register (edram) enables refresh cycles, o perating off the processor internal clock. if the processor is in power - save mode, the rcu must be reconfigured for the new clock rate. if the hlda pin is asserted when a refresh request is initiated (indicating a bus hold condition), the processor disabl es the hlda pin to allow a refresh cycle to be performed. the external circuit bus master must deassert the hold signal for at least one clock period to permit the execution of the refresh cycle. 4.16 interrupt control interrupt requests originate from a varie ty of internal and external sources that are arranged by the internal interrupt controller in priority order and presented one by one to the processor.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 146 1 - 888 - 824 - 4184 six external interrupt sources five maskable ( int4 C int0 ) and one nonmaskable (nmi) are connected to th e processor and six internal interrupt sources (three timers, two dma channels, and the asynchronous serial port that are not brought out to external pins). the five external maskable interrupt request pins can be used as direct interrupt requests. howev er, should more interrupts be needed, int3 C int0 may be used with the 82c59a - compatible external interrupt controller. by programming the internal interrupt controller to slave mode, a n 82c59a - compatible external interrupt controller can be used as the sys tem master. interrupt nesting can be used in all cases that permit interrupts of a higher priority to interrupt those of a lower priority. when an interrupt is accepted, other interrupts are disabled, but may be re - enabled by setting the interrupt enable flag ( if ) in the processor status flags register during the interrupt service routine (isr). setting if permits interrupts of equal or greater priority to interrupt the currently running isr. further interrupts from the same source will be blocked until the corresponding bit in the in - service register (inserv) is cleared. special fully nested mode ( sfnm ) is invoked for int0 and int1 by the sfnm bit in the int0 and int1 control register , respectively, when this bit is set to 1. in this mode , a new inter rupt may be generated by these sources regardless of the in - service bit. the following table shows the priorities of the interrupts at por . 4.16.1 interrupt types table 14 presents interrupt names, types, vector table address, end - of - interrupt (eoi) type, overal l priority, and related instructions. table 14 . interrupt types interrupt name interrupt type vector table address eoi type overall priority related instructions divide error exception a 00h 00h na 1 div, idiv trace interrupt b 01 h 04h na 1a all non - maskable interrupt (nmi) 02h 08h na 1b C breakpoint interrupt a 03h 0ch na 1 int3 int0 detected overflow exception a 04h 10h na 1 int0 array bounds exception a 05h 14h na 1 bound unused opcode exception a 06h 18h na 1 undefined opcodes esc opcode exception a,c 07h 1ch na 1 esc opcodes timer 0 interrupt d,e 08h 20h 08h 2a C timer 1 interrupt d,e 12h 48h 08h 2b C timer 2 interrupt d,e 13h 4ch 08h 2c C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 146 1 - 888 - 824 - 4184 note : if the priority levels are not changed , the default priority level will be used for the interrupt sources. a instruction execution generates interrupts. b performed in the same manner as for the 8086 and 8088. c an e sc opcode causes a trap. d because o nly one irq is generated for the three timers, they share priority level with respect to other sources. the timers have an interrupt priority order among themselves (2a > 2b > 2c). e these interrupt types are programmable in slave mode. f not available in slave mode. 4.17 timer control the ia 186er and ia 188er each have three 16 - bit programmable timers. timer 0 and timer 1 each has an input and output connected to external pins that permits it to count or to time events as well as to produce variable duty - cycle waveforms or non - repetitive waveforms. timer 1 can also be configured as a watchdog timer. because timer 2 does not have external connections, it is confined to internal functions such as real - time coding, time - delay appl ications, a prescaler for timer 0 and timer 1 , or to synchronize dma transfers. the peripheral control block contains eleven 16 - bit registers to control the programmable timers. each timer - count register holds the present value of its associated timer and may be read from or written to whether or not the timer is in operation. the microcontroller increments the value of the timer - count register when a timer event takes place. the value stored in a timers associated maximum count register determines its maximum count value. upon reaching it, the timer count register is reset to 0 in the same clock cycle that this count was attained. the timer count register does not store this maximum value. both timer 0 and timer 1 have a primary and a secondary maxim um count register that permits each to alternate between two discrete maximum values. timer 0 and timer 1 may have the maximum count registers configured in either primary only or both primary and secondary. if the primary only is configured to operate, o n reaching the reserved 09h - C C C dma 0 interrup t e 0ah 28h 0ah 3 C dma 1 interrupt e 0bh 2ch 0bh 4 C int0 interrupt 0ch 30h 0ch 5 C int1 interrupt 0dh 34h 0dh 6 C int2 interrupt 0eh 38h 0eh 7 C int3 interrupt 0fh 3ch 0fh 8 C int4 interrupt f 10h 40h 10h 9 C watchdog timer interrupt f 11h 44h 11h 9 C asynchronous serial port interrupt f 14h 50h 14h 9 C reserved 15h C 1fh 54h C 7ch C C C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 53 of 146 1 - 888 - 824 - 4184 maximum count, the output pin will go low for one clock period. if both the primary and secondary registers are enabled, the output pin reflects the state of the register in control at the time. this generates the required waveform that is dependent on the two values in the maximum count registers. because they are polled every fourth clock period, the timers can operate at a quarter of the internal clock frequency. although an external clock may be used, the timer output may take six cloc k cycles to respond to the input. 4.18 direct memory access (dma) dma frees the cpu from involvement in transferring data between memory and peripherals over either one or both high - speed dma channels. data may be transferred from memory to i/o, i/o to memory, memory to memory, or i/o to i/o. dma channels can be connected to the asynchronous serial port. the ia 186er supports the transfer of both bytes and words to and from even or odd addresses. it does not support word transfers to memory that is configured for byte accesses. the ia 188er does not support word transfers at all. each data transfer will take two bus cycles (a minimum of 8 clock cycles). there are four sources of dma requests for both dma channels: the channel request pin ( drq1 C drq0 ) timer 2 t he system software asynchronous serial port each channel may be programmed to have a different priority either to resolve a simultaneous dma request or to interrupt a transfer on the other channel. 4.19 dma operation the pcb contains six registers for each dma channel to control and specify the operation of the channel: two registers to store a 20 - bit source address two registers to store a 20 - bit destination address one 16 - bit transfer - count register one 16 - bit control register the number of dma transfers requ ired is designated in the dma transfer count register and may contain up to 64 kbytes or words. it will end automatically. dma channel function is
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 54 of 146 1 - 888 - 824 - 4184 defined by the control registers. like the other five registers, these may be changed at any time (includi ng during a dma transfer) and are implemented immediately. 4.20 dma channel control registers see section 5.1. 9 , d1con (0dah) and d0con (0cah) . t he dma channel control registers specify the following: whether the data destination is in memory or i/o space (bit [15]) whether the destination address is incremented, decremented, or unchanged after each transfer (bits [14 C 13]) whether the data source is in memory or i/o space (bit [12]) whether the source address is incremented, decremented, or unchanged after each transfer (bits [11 C 10]) whether dma transfers cease upon reaching a designated count (bit [9]) whether the last transfer generates an interrupt (bit [8]) synchronization mode (bits [7 C 6]) the relative priority of one dma channel with respect to the other (bit [5]) acceptance of dma requests from timer 2 (bit [4]) byte or word transfers (bit [0]) 4.21 dma priority with the exception of word accesses to odd memory locations or between locked memory addresses, dma transfers have a higher priority than cpu transfe rs. because the cpu cannot access memory during a dma transfer and a dma transfer cannot be suspended by an interrupt request, continuous dma activity will increase interrupt delay. an nmi request halts any dma activity, however, enabling the cpu to resp ond promptly to the request. 4.22 asynchronous serial port the asynchronous serial port employs standard industry communication protocols in its implementation of full duplex, bi - directional data transfers. the port can be either the source or destination of d ma transfers.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 55 of 146 1 - 888 - 824 - 4184 the following features are supported: full - duplex data transfers 7 - or 8 - bit data transfers odd, even, or no parity one or two stop bits error detection provided by parity, framing, or overrun errors dma to and from the port the port has it s own maskable interrupt t he port has an independent baud - rate generator maximum baud rate is 1/32 of the processor clock transmit and receive lines are double - buffered in power - save mode the baud rate generator divide factor must be re - programmed to compe nsate for the change in clock rate. 4.23 synchronous serial port the synchronous serial port allows the microcontrollers to communicate with asics that are required to be programmed but have a pin shortage. the four - pin interface allows half - duplex, bi - directi onal data transfer at a ma ximum of 25 mbits/sec . the synchronous serial interface of the ia 186er / ia 188er operates as the master port in a master/slave arrangement. there are four pins in the synchronous serial interface for communication with the system elements. these pins are two enables (sden0 and sden1), a clock (sclk) , and a data pin (sdata). in power - save mode, the baud rate generator divide factor must be re - programmed to compensate for the change in clock rate. 4.24 programmable i/o (pio) thirty - two pins are programmable as i/o signals (pio). table 15 presents them in both numeric and alphabetic order. because programming a pin as a pio disables its normal function, it should be done only if the normal function is not required. a pio pin can be pro grammed as an input or output with or without a weak pull - up or pull - down. a pio pin can be also programmed as an open - drain output. each pio pin regains default status after a por.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 56 of 146 1 - 888 - 824 - 4184 table 15 . default status of pio pins at reset pio no. associated pin power - on reset status associated pin pio no. power - on reset status 0 tmrin1 input with pull - up a17 7 normal operation a 1 tmrout1 input with pull - down a18 8 normal operation a 2 pcs6_n/a2 input with pull - up a19 9 normal opera tion a 3 pcs5_n/a1 input with pull - up den_n 5 normal operation a 4 dt/r_n normal operation a drq0 12 input with pull - up 5 den_n normal operation a drq1 13 input with pull - up 6 srdy normal operation a dt/r_n 4 normal operation a 7 b a17 normal operation a int2 31 input with pull - up 8 b a18 normal operation a int4 30 input with pull - up 9 b a19 normal operation a mcs0_n 14 input with pull - up 10 tmrout0 input with pull - down mcs1_n 15 input with pull - up 11 tmrin0 input with pull - up mcs2_n 24 input with pul l - up 12 drq0 input with pull - up mcs3_n/rfsh_n 25 input with pull - up 13 drq1 input with pull - up pcs0_n 16 input with pull - up 14 mcs0_n input with pull - up pcs1_n 17 input with pull - up 15 mcs1_n input with pull - up pcs2_n 18 input with pull - up 16 pcs0 _n input with pull - up pcs3_n 19 input with pull - up 17 pcs1_n input with pull - up pcs5_n/a1 3 input with pull - up 18 pcs2_n input with pull - up pcs6_n/a2 2 input with pull - up 19 pcs3_n input with pull - up rxd/pio28 28 input with pull - up 20 sclk input wi th pull - up s6/clk sel1_n 29 input with pull - up b,c 21 sdata input with pull - up sclk 20 input with pull - up 22 sden0 input with pull - down sdata 21 input with pull - up 23 sden1 input with pull - down sden0 22 input with pull - down 24 mcs2_n input with pull - up sden1 23 input with pull - down 25 mcs3_n/rfsh_n input with pull - up srdy 6 normal operation d 26 b,c uzi_n /clksel2_n input with pull - up tmrin0 11 input with pull - up 27 txd/pio27 input with pull - up tmrin1 0 input with pull - up 28 rxd/pio28 input with pull - up tmrout0 10 input with pull - down 29 b,c s6/clk sel1_n input with pull - up tmrout1 1 input with pull - down 30 int4 input with pull - up txd/pio27 27 input with pull - up 31 int2 input with pull - up uzi_n /clksel2_n 26 input with pull - up a input with pul lup option available when used as pio. b emulators use these pins and also a15 C a0 , ad15 C ad0 (ia 186er ), ale, bhe_n (ia 186er ) , clkouta, nmi, res_n, and s2_n C s0_n. c if bhe_n/aden_n (ia 186er ) or rfsh_n/aden_n (ia 188er ) is held low during por, these pins will r evert to normal operation. d input with pulldown option available when used as pio.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 57 of 146 1 - 888 - 824 - 4184 these default status setting s may be changed as desired. after por, a19 C a17 , the three most significant bits of the address bus, start with their normal function, allowin g the processor to begin fetching instructions from the boot address ffff0h. normal function is also the default setting for dt/r_n , den_n , and srdy after por. if the ad15 C ad0 bus override is enabled , s6/clk sel1 _n and uzi_n /clksel2_n automatically return to normal operation. the ad15 C ad0 bus override is enabled if either the bhe_n/aden_n for the ia 186er or the rfsh2_n/aden_n for the ia 188er is held low during por. 4.25 watchdog timer the wdt operates in real wdt fashion and may be used to prevent loss of con trol in the event that software does not respond in an expected manner. the wdt is active after reset, has a maximum timeout count, and is programmed for system reset mode. the wdt control register (wdtcon) may be written to only once after reset. this is accomplished by writing 3333h, then cccch followed by the new configuration data to the wdtcon register. provided they do not include access to the wdtcon register, any number of operations may be performed between these two words, including memory and i/o reads and writes. writing aaaah then 5555h to the wdtcon register resets the current count. this count cannot be read. provided they do not include access to the wdtcon register, any number of operations may be performed between these two words, i ncluding memory and i/o reads and writes. use of these sequences is intended to prevent executing code from blocking a wdt event. with the wdt, a maximum 1. 34 - second timeout period is possible in a 5 0 - mhz system. the wdt can be programmed to generate eit her an nmi or a system reset when it times out. if programmed to generate an nmi, the nmiflag (bit [12]) in the wdtcon register will be set when it occurs. this flag should be tested by the nmi interrupt service routine (isr) to establish whether the wdt or an external source generated the interrupt. if set by writing the 3333h and cccch sequence followed by the configuration data that includes clearing nmiflag, the isr should clear this flag. if the nmiflag is set while a second wdt timeout occurs, a w dt system reset is generated in place of a second nmi interrupt. the rstflag (bit [13]) in the wdtcon register is set if a wdt reset is generated, due to one wdt occurrence while the wdt is programmed to generate resets, or because a wdt event occurred wit h the nmiflag set. this permits system initialization code to distinguish between a wdt reset and hardware reset and take appropriate action. the rstflag is cleared by a read or write to the wdtcon register. during a wdt reset, the external pins are not re - sampled, ensuring that clocking, reset configuration register, and any other features that are user programmable during reset do not change when a wdt system reset occurs. all other activities are the same as those of a normal system reset.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 58 of 14 6 1 - 888 - 824 - 4184 4.26 internal memory integrated 32 kbyte of internal ram provides the same performance as zero wait state external memory. this memory is configured with an internal chip select register. 5. peripheral architecture 5.1 control and registers the on - chip peripherals in the ia 1 86er /ia 188er are controlled from a 256 - byte block of internal registers. although these registers are actually located in the peripherals they control, they are addressed within a single 256 - byte block of i/o space and are treated as a functional unit. a list of these registers is presented in table 16. w rite operations performed on the ia 188er should be 8 - bit writes, resulting in 16 - bit data transfers to the peripheral control block (pcb) register. only word reads should be performed to the pcb registe rs. if unaligned read and write accesses are performed on either the ia 186er or ia 188er , indeterminate behavior may result. note: adhere to these instructions while writing code to avoid errors.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 59 of 146 1 - 888 - 824 - 4184 table 16 . peripheral control re gisters register name offset register name offset peripheral control block registers timer registers pcb relocation register feh timer 2 mode and control register 66h reset configuration register f6h timer 2 max count compare a register 62h proces sor release level register f4h timer 2 count register 60h power - save control register f0h timer 1 mode and control register 5eh watchdog timer e6 h enable rcu register e4h timer 1 max count compare b register 5ch clock prescaler register e2h time r 1 max count compare a register 5ah memory partition register e0h timer 1 count register 58h dma registers timer 0 mode and control register 56h dma1 control register dah timer 0 max count compare b register 54h dma1 transfer count register d8h ti mer 0 max count compare a register 52h dma1 destination address high register d6h timer 0 count register 50h dma1 destination address low register d4h interrupt registers dma1 source address high register d2h serial port interrupt control register 44 h dma1 source address low register d0h watchdog timer control register 42h dma0 control register cah int4 interrupt control register 40h dma0 transfer count register c8h int3 interrupt control register 3eh dma0 destination address high register c6h int2 interrupt control register 3ch dma0 destination address low register c4h int1 interrupt control register 3ah dma0 source address high register c2h int0 interrupt control register 38h dma0 source address low register c0h dma1 interrupt control r egister 36h chip - select registers dma0 interrupt control register 34h internal memory chip select register ac h pcs_n and mcs_n auxiliary register a8h timer interrupt control register 32h mid - range memory chip - select register a6h interrupt status register 30h peripheral chip - select register a4h interrupt request register 2eh low - memory chip - select register a2h interrupt in - service register 2ch upper - memory chip - select register a0h interrupt priority mask register 2ah asynchronous serial port register interrupt mask register 28h serial port baud rate divisor register 88h interrupt poll status register 26h serial port receive register 86h interrupt poll register 24h serial port transmit register 84h end - of - interrupt (eoi) register 22h s erial port status register 82h interrupt vector register 20h serial port control register 80h serial port 1 registers pio registers synchronous serial receive register 18h pio data 1 register 7ah synchronous serial transmit 0 register 16h pio direc tion 1 register 78h synchronous serial transmit 1 register 14h pio mode 1 register 76h synchronous serial enable register 12h pio data 0 register 74h synchronous serial status register 10h pio direction 0 register 72h pio mode 0 register 70h
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 60 of 146 1 - 888 - 824 - 4184 5.1.1 relreg (0feh) the peripheral control block rel ocation reg ister maps the entire peripheral control block register bank to either i/o or memory space. in addition, relreg contains a bit that places the interrupt controller in either master or slave mode. the relreg contains 20ffh at reset (see table 17). table 17 . peripheral control block rel ocation reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved s/mn reserved io/mn ra 19 C ra 8 bi t [ 15 ] reserved. bit [ 14 ] s/mn when set to 1 , this bit places the interrupt controller into slave mode. when 0 , it is in master mode. bi t [13] reserved. b it [ 12 ] io/mn when set to 1 , the peripheral control block is mapped into memory space. when 0, this bit maps the peripheral co ntrol block register bank into io space. b its [ 11 C 0 ] ra19 C ra8 sets the base address (upper 12 bits) of the peripheral con trol bloc k register bank. ra 7 C ra 0 default to 0 . when b it [ 12 ] ( io/mn ) is set to 1 , ra19 C ra 16 are ignored. 5.1.2 rescon (0f6h) the res et con figuration register latches user - defined information present at specified pins at the rising edge of reset. the contents of this register are read - only and remain valid until the next reset. the rescon contains user - defined information at reset (see table 18) . table 18 . reset configuration reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rc15 C rc 0 b its [ 15 C 0 ] rc15 C rc0 at the rising edge of reset, the values of specified pins (ad15 C ad0 for the ia 186er and ao 15 C ao8 and ad 7 C ad 0 for the ia 188er ) are latched into this register.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 61 of 146 1 - 888 - 824 - 4184 5.1.3 prl (0f4h) the p rocessor r elease l evel register contains a code corresponding to the latest pr ocessor production release. the prl is a read - only register . the prl contains a800h for ia186er and a900h for ia188er. see table 19 . table 19 . p rocessor r elease l evel register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prl 7 C prl 0 res erved b its [ 15 C 8 ] prl7 C prl0 the latest processor release level. prl value processor release level a8 186 a9 188 bits [7 C 0] reserved. 5.1.4 pdcon (0f0h) the power - save control register controls several miscellaneous system i/o and timing functions. the pd con contains 0000h at reset ( see table 20). table 20 . power - save control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 psen reserved cbf cbd caf cad reserved f2 f1 f0 bit [ 15 ] psen when set to 1, enables the power - save mode causing the internal operati ng clock to be divided by the value in f2 C f0 . external interrupts or interrupts from internal interrupts automatically clear psen . software interrupts and exception do not clear psen . note : t he value of psen is not restored upon execution of an iret inst ruction. bit s [ 14 C 12] reserved these bits read back as 0 . bit [ 11 ] cbf when set to 1, the clkoutb output follows the input crystal (pll) frequency. when 0, it follows the internal clock frequency after the clock divider. b it [ 10 ] cbd when set to 1, the clkoutb output is tri - state d . when 0, it is driven as an output per the cbf bit.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 62 of 146 1 - 888 - 824 - 4184 bit [ 9 ] caf when set to 1, the clkouta output follows the input crystal (pll) frequency. when 0, it follows the internal clock frequency after the clock divider. bit [ 8 ] cad when set to 1, the clk outa output is tri - stated . when 0, it is driven as an output per the c a f bit. bi ts [ 7 C 3 ] reserved these bits read back as 0 . bits [ 2 C 0 ] f2 C f0 these bits control the clock divider as shown below. note: psen must be 1 for the clock divider to functio n. f2 f1 f0 divider factor 0 0 0 divide by 1 (2 0 ) 0 0 1 divide by 2 (2 1 ) 0 1 0 divide by 4 (2 2 ) 0 1 1 divide by 8 (2 3 ) 1 0 0 divide by 16 (2 4 ) 1 0 1 divide by 32 (2 5 ) 1 1 0 divide by 64 (2 6 ) 1 1 1 divide by 128 (2 7 ) 5.1.5 wdtcon (0e6h) the w atch d og t i mer con trol register provides contr ol and status for the wdt. the wdtcon contains c080h at reset (see table 2 1 ). table 21 . w atch d og t imer con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ena wrst rstflag nmiflag test res count bit [ 15 ] ena when set to 1, the wdt is enabled. when 0, it is disabled. bit [ 14 ] wrst when set to 1, an internal wdt reset is generated when the wdt timeout count ( count ) is reached. when 0, an nmi will be generated once wdt timeout count is reached and the nmiflag bit is 0. if the nmiflag bit is 1, an internal wdt reset is generated when the wdt timeout count is reached. bit [ 13 ] rstflag when set to 1, a wdt timeout event has occurred. this bit may be cleared by software or by an external reset. bit [ 12 ] nmiflag when set to 1, a wdt nmi event has occurred. this bit may be cleared by software or by an external reset. if this bit is 1 when wdt timeout occurs, an internal wdt reset is generated regardless of the state of wrst .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 63 of 146 1 - 888 - 824 - 4184 bit [ 11 ] te st this bit is reserved for chip test and should be always set to 0. bits [ 10 C 8 ] reserved. bits [ 7 C 0 ] count control the timeout period for the wdt as follows: t timeout = 2 exponent / frequency (equation 1 ) where: t timeout = the wdt timeout period in seconds. frequency = the processor frequency in hertz. exponent = is based upon count as shown below: bit [ 7 ] bit [ 6 ] bit [ 5 ] bit [ 4 ] bit [ 3 ] bit [ 2 ] bit [ 1 ] bit [ 0 ] exponent 0 0 0 0 0 0 0 0 na x x x x x x x 1 10 x x x x x x 1 0 20 x x x x x 1 0 0 21 x x x x 1 0 0 0 22 x x x 1 0 0 0 0 23 x x 1 0 0 0 0 0 24 x 1 0 0 0 0 0 0 25 1 0 0 0 0 0 0 0 26 5.1.6 edram (0e4h) the e nable rcu register provides control and status for the refresh counter. the edram r egister contains 0000h at reset (see table 2 2 ). table 22 . e nable d ynamic ram refresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e reserved t8 C t 0 bit [ 15 ] e when set to 1, the refresh counter is enabled and m cs 3_n is configured to act as rfsh_n . clearing e emptie s the refresh counter and disables refresh requests. the refresh address is unaffected by clearing e . bits [14 C 9 ] reserved these bits read back as 0. bits [8 C 0 ] t8 C t0 these bits hold the current value of the refresh co unter. the y are read - only.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 64 of 146 1 - 888 - 824 - 4184 5.1.7 cdram (0e2h) the c lock prescaler register determines the period between refresh cycles. the count for dynamic ram ( cdram ) register is undefined at reset (see table 2 3 ). table 23 . c ount for dynamic ram refresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rc8 C rc 0 bits [ 15 C 9 ] reserved these bits read back as 0. bits [ 8 C 0 ] rc8 C rc0 these bits hold the clock count interval between refresh cycles. in power - save mode, the refresh counter value should be adjusted to account for the clock divider value in pd con. note: this value should not be set to less than 18 (12h), else there would never be sufficient bus cycles available for the processor to execute code. 5.1.8 m dram (0e0h) the m emory p artition register holds the a19 C a13 address bits of the 20 - bit base refresh address. the mdram regist er contains 0000h at reset (see table 2 4 ). table 24 . m emory partition for d ynamic ram refresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m6 C m 0 reserved bits [15 C 9 ] m6 C m0 upper bits corresponding to address bits a19 C a13 of the 20 - bit memory refresh address. these bits are not available on the a19 C a0 bus. when using psram mode, m6 C m0 must be programmed to 0000000b. bits [ 8 C 0 ] reserved these bits read back as 0 . 5.1.9 d1con (0dah) and d0con (0cah) d ma con trol registers. dma control registers control operation of the two dma channels. the d0con and d1con registers are fff9h at reset (see table 2 5 ) . table 25 . dma control registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm/ion ddec dinc sm/i o n sdec sinc tc int syn1 C syn0 p tdrq res chg st bn/w
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 65 of 146 1 - 888 - 824 - 4184 bit [ 15 ] dm/ion destination address space select selects memory or i/o space for the destination address. when dm/io is set to 1, the destination address is in memory space . w hen 0, it is in i/o space. bit [ 14 ] ddec destination decrement . when set to 1 , it automati cally decrements the destination address after each transfer. the address is decremented by 1 or 2 , depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 13 ] dinc destination increment . when set to 1, it automatically increments the destination address after each transfer. the address is incremented by 1 or 2 , depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decre ment bits are set to the same value (00b or 11b). bit [ 12 ] sm/ion source address space select selects memory or i/o space for the source address. when set to 1, the sou rce address is in memory space. when 0, it is in i/o space. bit [ 11 ] sdec source d ecrement . w hen set to 1, it automatically decrements the source address after each transfer. the address is decremented by 1 or 2, depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 10 ] sinc source increment. w hen set to 1, it automatically increments the source address after each transfer. the address is incremented by 1 or 2, depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does n ot change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 9 ] tc terminal count . the dma decrements the transfer count for each dma transfer. when set to 1, the source or destination synchronized dma transfers terminate when the count reaches 0. w hen 0, they do not. unsynchronized dma transfers always end when the count reaches 0, regardless of this bit s setting. bit [ 8 ] int interrupt. when this bit is set to 1 , the dma channel generates an interrupt request on comp letion of the transfer count. however, for an interrupt to be generated, the tc bit must also be set to 1. bits [ 7 C 6 ] syn1 C syn0 synchronization type bits select channel synchronization types as shown below . the value of these bits is ignored if tdrq (bit [4]) is set to 1. a processor reset causes these bits to be set to 11b.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 66 of 146 1 - 888 - 824 - 4184 synchronization bit channel selection syn1 syn0 sync type 0 0 unsynchronized 0 1 source synchronized 1 0 destination synchronized 1 1 reserved bit [ 5 ] p relative priorit y. when set to 1 , selects high priority for this channel relative to the other channel during simultaneous transfers. bit [ 4 ] tdrq timer 2 synchronization. when set to 1, enables dma requests from timer 2. when 0 , disables them . bit [ 3 ] reserved . bit [ 2 ] chg change start bit . this bit must be set to 1 to allow modification of the st bit during a write. during a write, when chg is set to 0, st is not changed when writing the control word. the result of reading this bit is always 0. bit [ 1 ] st sta rt/stop dma channel. when set to 1, the dma channel is started. the chg bit must be set to 1 for this bit to be modified during the register write. a processor reset causes this bit to be set to 0. bit [ 0 ] bn/w byte/word select. when set to 1, word t ransfers are selected. when 0, byte transfers are selected. note: word transfers are not supported if the chip selects are programmed for 8 - bit transfers. the ia 188er does not support word transfers 5.1.10 d1tc (0d8h) and d0tc (0c8h) d ma t ransfer c oun t registe rs. the dma transfer count registers are maintained by each dma channel. they are decremented after each dma cycle. the state of the tc bit in the dma control register has no influence on this activity. i f unsynchronized transfers are programmed or if the tc bit in the dma control word is set, dma activity ceases when the transfer count register reaches 0. the d0tc and d1tc registers are undefined at reset (see table 2 6 ) . table 26 . dma transfer count registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 67 of 146 1 - 888 - 824 - 4184 bits [ 15 C 0] tc 15 C tc 0 dma transfer count contains the transfer count for the respective dma channel. its value is decremented after each transfer. 5.1.11 d1dsth (0d6h) and d0dsth (0c6h) the d ma d e st ination address h igh register. the 20 - bit destination address consists of these 4 b its combined with the 16 bits of the respective destination address low register. a dma transfer requires that two complete 16 - bit registers (high and low registers) be used for both the source and destination addresses of each dma channel involved. thes e four registers must be initialized. each address may be incremented or decremented independently of each other after each transfer. the addresses are incremented or decremented by two for word transfers and incremented or decremented by one for byte tr ansfers. they are undefined at reset (see table 2 7 ) . table 27 . d ma d e st ination address high register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dda19 C dda16 bits [ 15 C 4 ] reserved. bits [ 3 C 0 ] dda19 C dda 16 dma destination add res s high bits are driven onto a19 C a 16 during the write phase of a dma transfer. 5.1.12 didstl (0d4h) and d0dstl (0c4h) d ma d e st ination address l ow register. the 16 bits of these registers are combined with the 4 bits of the respective dma destination address h igh register to produce a 20 - bit destination address. they are undefined at reset (see table 2 8 ) . table 28 . d ma d e st ination address l ow register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dda15 C dda0 bits [ 15 C 0] dda15 C dda0 dma destination addre ss low bits are driven onto a15 C a0 during the write phase of a dma transfer. 5.1.13 d1srch (0d2h) and d0srch (0c2h) d ma s ou rc e address h igh register. the 20 - bit source address consists of these 4 bits combined with the 16 bits of the res pective source address low register. a dma transfer requires that two complete 16 - bit registers in the pcb (high and low registers) be used for both the source and destination addresses of each dma channel involved. each channel requires that all four ad dress registers be initialized. each address may be independently incremented or
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 68 of 146 1 - 888 - 824 - 4184 decremented after each word transfer by 2 or by 1 for byte transfers. they are undefined at reset (see table 2 9 ) . table 29 . d ma s ou rc e address h igh register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dsa19 C dsa16 bits [ 15 C 4 ] reserved . bits [ 3 C 0 ] dsa 19 C dsa 16 dma source addres s high bits are driven onto a19 C a 16 during the read phase of a dma transfer. 5.1.14 d1srcl (0d0h) and d0srcl (0c0h) d ma s ou rc e address l ow register. the 16 bits of these registers are combined with the 4 bits of the respective dma source address high register to produce a 20 - bit source address. they are undefined at reset (see table 30 ) . table 30 . d ma s ou rc e address l ow register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsa15 C dsa0 bi ts [15 C 0] dsa15 C dsa 0 dma source address low bits are driven onto a15 C a0 during the read phase of a dma transfer. 5.1.15 imcs (0ach) internal memory chip select register. this register controls the generation of chip select for the internal r am . this memory can be mapped to any 32k byte boundary. an enable bit is used to activ ate the memory rather than any write to the register. a separate control bit allows reads from this memory to appear on the external bus. the value of this register is undefined at reset (see table 31). table 31 . internal memory chip select register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 C ba13 sr re reserved bi ts [15 C 11 ] base address upper five bits of 20 - bit memory address to which internal memory is mapped . undefined at reset . bi t [10 ] sr (show read) when high, drives data on the external ad bus during read of internal memory . zero at reset.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 69 of 146 1 - 888 - 824 - 4184 bi ts [9 ] en (internal ram enable) internal memory is enabled by writing this bit to a 1 and initializing the base address. this bit is a zero at reset. 5.1.16 mpcs (0a8h) mcs and pcs (mpcs) auxiliar y register. because this register controls more than one type of chip select, it is unlike ot her chip select control registers. the mpcs register contains information for mcs3_n C mcs0_n , pcs6_n C pcs5_n , and pcs3_n C pcs0_n . the mpcs register also contains a bit that configures the pcs6_n C pcs5_n pins as either chip selects or as alternate sources for the a2 and a 1 address bits. either a 2 / a 1 or pcs6_n C pcs5_n are selected to the exclusion of the other. when programmed for address bits, these outputs can be used to provide latched address bits for a2 and a1 . the pcs6_n C pcs5_n pins are high and n ot activ e on processor reset. when the pcs6_n C pcs5_n are configured as address pins , an access to the mpcs register causes them to activate . they do not require corresponding access to the pacs register to be activated. the value of the mpcs register is undefin ed at reset (see table 3 2 ) . table 32 . mcs and pcs auxiliar y register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 m6 C m0 ex ms reserved r2 r1 C r0 bit [ 15 ] reserved set to 1. bits [ 14 C 8 ] m 6 C m 0 mcs_n block size these seven bits determine the to tal memory block size for the mcs3_n C mcs0_n chip selects. the size is divided equally among the m . the relationship between m 6 C m 0 and the size is shown below . select sizes of m6 C m0 by total block size total block size individual select size m6 C bit [ 7 ] ex pin selector this bit determines whethe r the pcs6_n C pcs5_n pins are configured as chip selects or as alternate outputs for a2 and a1 . when set to 2 ,
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 70 of 146 1 - 888 - 824 - 4184 they are configured as peripheral chip select pins . w hen 0, they become address bit s a 2 and a 1 , respectively. bit [ 6 ] ms memory/ i/o space selec tor this bit determines whether the pcs_n pins are active during either memory or i/o bus cycles. when set to 1, the outputs are active for memory bus cycles . w hen 0, they are active for i/o bus cycles. bits [ 5 C 3 ] reserved set to 1. bit [ 2 ] r2 ready mode this bit influences only the pcs6_n C pcs5_n chip selects. when set to 1, external ready is ignored. when 0, it is required. bits [ 1 C 0 ] r 1 C r 0 wait - state value these bits influence only the pcs6_n C pcs5_n chip selects. the ir value determines the nu mber of wait states inserted into an access . up to three wait states can be inserted ( r1 C r0 = 00b to 11b). 5.1.17 mmcs (0a6h) m idrange m emory c hip s elect (mmcs) register. four chip - select pins, mcs3_n C mcs0_n , are provided for use within a user - locatable memory block. excluding the areas associated with the ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip selects, pcs6_n C pcs5_n and pcs3_n C pcs0_n ) , the memory block base address can be located anywhere within the 1 - mb yte memory address space. if the pcs_n chip selects are mapped to i/o space , the mcs_n address range can overlap the pcs_n address range. two registers program the midrange chip selects. the mmcs register determines the base address, the ready condition , and wait states of the memory block that are accessed through the mcs_n pins. the pcs_n and mcs_n auxiliary (mpcs) register configures the block size. on reset , the mcs3_n C mcs0_n pins are not active. b oth the m mcs and mpcs registers must be written to activate these chip selects. unlike the ucs_n and lcs_n chip selects , the mcs3_n C mcs0_n outputs assert with the multiplexed ad address bus ( ad15 C ad0 for the ia 186er and ao 15 C ao8 and ad 7 C ad 0 for the ia 188er ) , rather than the earlier timing of the a19 C a0 bus . if the a19 C a0 bus is used for address selection , the timing is delayed for a half cycle later than that for ucs_n and lcs_n . the value is undefined at reset (see table 3 3 ) . table 33 . m idrange m emory c hip s elect register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 C ba13 reserved r2 r1 C r0 bits [ 15 C 9 ] ba19 C ba13 base address the value of the this pin determines the base address of the memory block that is addressed by the mcs_n chip select pins. these bits
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 71 of 146 1 - 888 - 824 - 4184 correspond to a19 C a13 of the 20 - bit memory address. the remaining bits a12 C a0 of the base address are always 0. C the base address may be any integer multiple of the size of the memory clock selected in the mpcs register. for example, if the midrange block is 32 kbytes, the bl ock could be located at 20000h or 28000h but not at 24000h. C if the lcs_n chip select is inactive, the base address of the midrange chip selects can be set to 00000h, because the lcs_n chip select is defined to be 00000h but is unused. because the base add ress must be an int eger multiple of the block size, a 512k mmcs block size can only be used with the lcs_n chip select inactive and the base address of the midrange chip selects set to 00000h. bits [ 8 C 3 ] reserved set to 1. bit [ 2 ] r2 ready mode this bi t determines the mcs_n chip select ready mode. when set to 1, an external ready is ignored. when 0, it is necessary. in each case, the number of wait states inserted in an access is determined by the value of the r1 and r0 bits. bits [1 C 0 ] r 1 C r 0 wait - state value. the value of the se bits determines the number of wait states inserted in an access. up to three wait states can be inserted ( r1 C r0 = 00b to 11b). 5.1.18 pacs (0a4h) p eripher a l c hip s elec t register. the se peripheral chip selects are asserted over a 256 - byte range with the same timing as the ad address bus. there are six chip selects, pcs6_n C pcs5_n and pcs3_n C pcs0_n , that are use d in either the user - locatable memory or i/o blocks. the pcs4_n chip select is not implemented in the ia 186er or ia 188er . excluding the areas use d by the ucs_n, lcs_n, and mcs_n chip selects, the memory block can b e located anywhere within the 1 - mbyte address space. these chip selects may also be configured to access the 64 - kbyte i/o space. programming the peripheral chip selects uses the peripheral chip select (pacs) and the pcs_n and mcs_n auxiliary (mpcs) register s . the pacs register establishes the base address, configures the ready mode, and determines the number of wait states for the pcs3_n C pcs0_n outputs. the mpcs register configures the pcs6_n C pcs5_n pins to be either chip selects or address pins a1 and a2 . when these pins are configured as chip selects, the mpcs register determines the ready and wait states for these output pins and whether they are active durin g memory or i/o bus cycles. these pins are activated as chip selects by writing to the two registers (pacs and mpcs). the y are not active on reset. to configure and activate them as address pins, it is
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 72 of 146 1 - 888 - 824 - 4184 necessary to write to both the pacs and mpcs regist ers. pins pcs6_n C pcs5_n can be configured for 0 to 3 wait states and pcs3_n C pcs0_n can be programmed for 0 to 15 wait states. the value of the pacs register is undefined at reset (see table 3 4 ) . table 34 . p eripher a l c hip s elec t register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 C ba11 reserved r3 r2 r1 C r0 bits [ 15 C 7 ] ba 19 C ba 11 base address bits correspond to bits [ 19 C 11 ] of the 20 - bit programmable base address of the peripheral chip select block and determine the base address. because i/o addresses are only 16 bits wide , if the pcs_n chip selects are mapped to i/o space, bits ba19 - 16 must be set to 0000b. the pcs address ranges are shown below. address ranges of pcs chip selects p cs _ n line range low high pcs0 _ n base address base address + 255 pcs1 _ n base address + 256 base address + 511 pcs2 _ n base address + 512 base ad dress + 767 pcs3 _ n base address + 768 base address + 1023 reserved n a n a pcs5 _ n base address + 1280 base address + 1535 pcs6 _ n base address + 1536 base address + 1791 bits [ 6 C 4 ] reserved set to 1. bit [ 3 ] r 3 wait state value. s ee pcs3_n C pcs0_n wait - state encoding shown below . pcs3 _ n C pcs0 _ n wait - state encoding r3 r1 r0 wait states 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 5 1 0 1 7 1 1 0 9 1 1 1 15 bit [ 2 ] r 2 ready mode. when set to 1, external ready is ignored. when 0, it is required. i n each case the number of wait states is determined according to the pcs3_n C pcs0_n wait - state encoding shown above .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 73 of 146 1 - 888 - 824 - 4184 bits [ 1 C 0 ] r 1 C r 0 wait - state value (s ee pcs3_n C pcs0_n wait - state encoding above) . the pcs6_n C pcs5_n and pcs3_n C pcs0_n pins are multiplexed with the pio pins. f or these to function as chip selects, the pio mode and direction settings for these pins must be set to 0 for normal operation. 5.1.19 lmcs (0a2h) the low - memory chip select (l mcs) register configures the lmcs provided to facilitate access to the interrupt vector table located at 00000h or the bottom of memory. the lcs_n pin is not enabled at reset. the lcs_n pin is enabled by any write to the lmcs register . the value of the l mcs register is undefined at reset except da, which is set to 0 (see table 3 5 ) . table 35 . low - memory chip select register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res ub2 C ub0 reserved da pse reserved r2 r1 C r0 bit [ 15 ] reserved s et to 0 . bits [ 14 C 12 ] ub2 C ub 0 upper boundary . these bits define the upper boundary of memory accessed by the lcs_n chip select. the list below presents the possible block - size configurations ( a 512 - kbyte max imum ). lmcs block - size programming values mem ory block size ending address ub2 C ub0 64k 0ffffh 000b 128k 1ffffh 001b 256k 3ffffh 011b 512k 7ffffh 111b bits [ 11 C 8 ] reserved set to 1. bit [ 7 ] da disable address . when set to 1, the multiplexed address bus is disabled, providing reduced power consumption . when 0, the address is driven onto the address bus ad15 C ad0 during the address phase of a bus cycle. this bit is set to 0 at reset. C if bhe_n/aden_n (ia 186er ) is held at 0 during the rising edge of res_n , the address bus is always driven, reg ardless of the setting of da.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 74 of 146 1 - 888 - 824 - 4184 bit [ 6 ] pse psram mode enable . when set to 1 , psram support for the lcs_n chip select memory space is enabled. the edram, mdram, and cdram rcu registers must be configured for auto refresh before psram support is enabled. setting the enable bit (en) in the enable rcu register (edram, offset e4h) configures the mcs3_n/rfsh_n as rfsh_n . bits [ 5 C 3 ] reserved set to 1. b it [ 2 ] r2 ready mode . when set to 1, the external ready is ignored. when 0, it is required. the value of r1 C r0 bits determines the number of wai t states inserted. bits [ 1 C 0 ] r 1 C r 0 wait - state value. the value of these bits determines the number of wait states inserted into an access to the lcs_n memory area. this number ranges from 0 to 3 (r1 C r0 = 00b to 11b) . 5.1.20 umcs (0a0h) the u pper m emor y c hi p s elect register configures the umcs pin, used for the top of memory. on reset, the first fetch takes place at memory location ffff0h and thus this area of memory is usually used for instruction memory. the ucs_n defaults to an active state at reset wit h a memory range of 64 kbytes (f0000h to fffffh), external ready required, and three wait states automatically inserted. the upper end of the memory range always ends at fffffh. the lower end of this upper memory range is programmable. the value of the umcs register is f03bh at reset (see table 3 6 ) . table 36 . u pper - m emor y c hip s elect register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 lb2 C lb0 reserved da 0 reserved r2 r1 C r0 bit [ 15 ] reserved set to 1. bits [ 14 C 12 ] lb 2 C lb 0 lowe r boundary these bits determine the bottom of the memory accessed by the ucs_n chip select . the umcs block - size programming values shown below list the possible block - size configurations ( a 512 - kbyte max imum ) . umcs block - size programming values memory block size starting address lb2 C C C C bits [ 11 C 8 ] reserved.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 75 of 146 1 - 888 - 824 - 4184 bit [ 7 ] da disable address . when set to 1, the multiplexed address bus is disabled and the address is not driven on the address bus when ucs_n is asserted, providing reduced power consumption . when 0 , the address is driven onto the address bus ( ad15 C ad0 ) during the address phase of a bus cycle when ucs_n is asserted. this bit is set to 0 at reset. C if bhe_n/aden_n (ia 186er ) is held at 0 during the rising edge of res_n , the address bus is always driven, regardless of the setting. bit [ 6 ] reserved set to 0. bit s [ 5 C 3 ] rese rved set to 1. bit [ 2 ] r2 ready mode when set to 1, the external ready is ignored. when 0, it is required. the value of the r1 C r0 bits determines the number of wait states inserted. bits [ 1 C 0 ] r1 C r0 wait - state value the value of these bits determines the number of wait states inserted into an access to the lcs_n memory area. this number ranges from 0 to 3 ( r1 C r0 = 00b to 11b). 5.1.21 spbaud (088h) s erial p ort baud rate divisor register. the value in this register determines t he number of internal processor cycles in one phase (half - period) of the 32 x serial clock. the contents of these registers must be adjusted to reflect the new processor clock frequency if power - save mode is in effect. the baud rate divisor may be calcul ated from: b auddiv = (processor frequency/(32 x baud rate)) - 1 (equation 2 ) by setting the bauddiv to 0000h, the maximum baud rate of 1/32 of the internal processor frequency clock is set. setting bauddiv to 129 (81h) provides a baud rate of 9600 at 40 mhz. the baud rate tolerance is +4.6% to C 1.9% with respect to the actual serial port baud rate, not the target baud rate (see table 3 7 ). table 37 . baud rates baud rate divisor based on cpu clock rate 20 mhz 25 mhz 33 mhz 40 mhz 300 4166 5208 6875 8333 600 2083 2604 3437 4166 1200 1041 1302 1718 2083 2400 520 651 859 1041 4800 260 325 429 520 9600 130 162 214 260 14400 42 53 71 85
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 76 of 146 1 - 888 - 824 - 4184 19200 31 39 53 64 625 kbaud 0 na na 1 781.25 kbaud na 0 na na 1.041 mbaud na na 0 na 1.25 mbaud na na na 0 the value of the spbaud register at reset is undefined (see table 3 8 ). table 38 . s erial p ort baud rate div isor registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bauddiv bits [ 15 C 0 ] bauddiv baud rate divisor defines the divisor for the internal processor clock. 5.1.22 sprd (086h) s erial p ort r eceive d ata register . data received over the serial port are stored in this register until read. the data are received initially by the receive s hift register (no software access) permitting data to be received while the previous data are being read. the rdr bit (receive data ready) in the serial port status register indicates the status of the sprd register. a 1 indicates there is valid data in t he receive register. the value of the sprd register is undefined at reset (see table 3 9 ) . table 39 . s erial p ort r eceive data register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rdata bits [ 15 C 8 ] reserved . bits [ 7 C 0 ] rdata holds valid data if the rdr bit of the status register is set. 5.1.23 sptd (084h) s erial p ort t ransmit d ata register. data is written to this register by software, with the values to be transmitted by the serial port. double buffering of the transmitter allow s for the transmission of data from the transmit shif t register (no software access) while the next data are written into the transmit register. the thre bit in the serial port status register indicates whether there is valid data in the sp td register. t he thre bit must be a 1 before writing data to this register to prevent overwriting valid data that is already in the sp td register. the value of the sptd register is undefined at reset (see table 40 ) .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 77 of 146 1 - 888 - 824 - 4184 table 40 . s erial p ort t rans mit data register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tdata bits [ 15 C 8 ] reserved . bits [ 7 C 0 ] tdata holds the data to be transmitted. 5.1.24 spsts (082h) s erial p ort st atu s register. this register stores information concerning the current status o f the port. the status bits are described below. the value of the spsts register is undefined at reset (see table 41 ). table 41 . s erial p ort st atu s register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved temt thre rdr brki fer per oer bits [ 15 C 7] reserved set to 0. bit [6] temt transmitter empty when both the transmit shift register and the transmit register are empty, this bit is set indicating to software that it is safe to disable the transmitter. this bit is read - only. bit [ 5 ] thre transmit holding register empty when this bit is 1, the corresponding transmit holding register is ready to accept data. this is a read - only bit. bit [ 4 ] rdr receive data ready when this bit is 1, the sprd register contains valid data. this is a read_only bit and ca n be reset only by reading the receive register. bi t [ 3 ] brki break interrupt this bit indicates that a break has been received when this bit is set to 1 and causes a serial port interrupt request , if rsie is set . note : this bit should be reset by softw are. bit [ 2 ] fer framing error detected when the receiver samples the rxd/pio28 line as low when a stop bit is expected (line high) , a framing error is generated setting this bit. note : this bit should be reset by software. bit [ 1 ] per parity error dete cted when a parity error is detected in either mode 1 or 3, this bit is set.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 78 of 146 1 - 888 - 824 - 4184 note: this bit should be reset by software. bit [ 0 ] oer overrun error detected when new data overwrites valid data in the receive register (because it has n o t been read) an o verrun error is detected setting this bit. note : this bit should be reset by software. 5.1.25 spct (080h) s erial p ort control register. this register controls both transmit and receive parts of the serial port. the value of the spct register is 0000h at reset (see table 4 2 ). table 42 . s erial p ort control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dma reserved txie rxie loop brk brkval pmode wlgn stp tmode rsie rmode bits [15 - 13] dma control field enables dma transfers to and from serial port as follows: dma bits receive transmit 000 no dma no dma 001 dma0 dma1 010 dma1 dma0 011 reserved 100 dma0 no dma 101 dma1 no dma 110 no dma dma0 111 no dma dma1 dma transfers to the serial port act as destination - synchronized transfers. dma request occurs when thre is set to 1. interrupts are disabled regardless of the state of txie when dma transfers are enabled. dma transfers from the serial port act as source - synchronized transfers. dma request o ccurs when rdr is set to 1. interrupts are disabled regardless of the state of rxie when dma transfers are enabled. bit [12] reserved set to 0. bit [11] txie transmitter ready interrupt enable this bit enables the generation of an interrupt request whenever the transmit holding register is empty ( thre bit [ 1 ] ). the
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 79 of 146 1 - 888 - 824 - 4184 respective port does not generate interrupts when this bit is 0. in terrupts continue to be generated as long as thre and the txie are 1. bit [10] rxie receive data ready interrupt enable this bit enables the gen eration of an interrupt request whenever the receive register contains valid data ( rdr bit [ 1 ] ). the respecti ve port does not generate interrupts when this bit is 0. interrupts continue to be generated as long as rdr and the rxie are 1. bit [9] loop loop back the serial port is placed into the loop - back mode when this bit is set. bit [ 8 ] brk send break when this bit is set to 1, the txd/pio27 pin is driven to the value in brkval , overriding any data that may be in the course of being shifted out of the transmit shift register. bit [ 7 ] brkval break value this is the value transmitted when brk is asserted. bits [6 C 5] pmode parity mode see table below . these bits define parity checking and generation 00 at reset. parity pmode none 0x odd 10 even 11 bit [4] wlgn word length the number of bits transmitted or received in a frame is determined by the val ue of this bit. when this bit is 1 , the numbe r of data bits in a frame is 8. when 0, it is 7 . this bit is 0 at reset. bit [ 3 ] stp stop bits this bit specifies the number of stop bits used to indicate the end of a frame. when this bit is 1, the number of stop bits is 2. when 0, it is 1. this bit is 0 at reset. bit [ 2 ] tmode transmit mode when this bit is 1, the transmit sectio n of the serial port is enabled. when 0, it is disabled. bit [ 1 ] rsie receive status interrupt enable when an exception o ccurs during data reception , an interrupt request is generated if enabled by this bit ( rsie = 1). interrupt requests are made for the error conditions listed in the serial port status register ( brk, oer, per, and fer ) . this bit is 0 at reset.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 80 of 146 1 - 888 - 824 - 4184 bit [ 0 ] rmo de receive mode when this bit is 1, the receive sectio n of the serial port is enabled. when 0, it is disabled. this bit is 0 at reset. 5.1.26 pdata1 (07ah) and pdata0 (074h) p io data registers. when a pio pin is configured as an output, the value in the corresponding pio da ta register bit is driven onto the pin. however, if the pio pin is configured as an input, the value on the pin is put into the corresponding bit of the pio data register. table 4 3 lists the default states for the pio pins. table 43 . pio pin assignments pio number associated pin name power - on reset status 0 tmrin1 input with pull - up 1 tmrout1 input with pull - down 2 pcs6/a 2 input with pull - up 3 pcs5/a 1 input with pull - up 4 dt/r_n normal operation a 5 den_n normal operation a 6 srdy normal operation b 7 c a17 normal operation a 8 c a18 normal operation a 9 c a19 normal operation a 10 tmrout0 input with pull - down 11 tmrin0 input with pull - up 12 drq0 input with pull - up 13 drq1 input with pull - up 14 mcs0_n input with pull - up 15 mcs1_n input with pull - up 16 pcs0_n input with pull - up 17 pcs1_n input with pull - up 18 pcs2_n input with pull - up 19 pcs3_n input with pull - up 20 sclk input with pull - up 21 sdata input with pull - up 22 sden0 input with pull - down 23 sden1 input with p ull - down
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 81 of 146 1 - 888 - 824 - 4184 table 4 3 . pio pin assignments (continued) pio number associated pin name power - on reset status 24 mcs2_n input with pull - up 25 mcs3_n/rfsh_n input with pull - up 26 c,d u zi /clksel2_n input with pull - up 27 txd/pio27 input with pull - up 28 rxd/p io28 input with pull - up 29 c,d s6/clk sel1 _n input with pull - up 30 int4 input with pull - up 31 int2 input with pull - up a when used as a pio pin, it is an input with a pull - up option available . b when used as a pio pin, it is an input with a pull - down option available . c emulators use these pins and also a15 C a0 , ad15 C ad0 (ia 186er ), ale, bhe_n (ia 186er ) , clkouta, nmi, res_n, and s2_n C s0_n. d if bhe_n/aden_n (ia 186er ) or rfsh2_n/aden (ia 188er ) is held low during por , these pins revert to normal operation. the va lue of the pdata registers is undefined at reset (see tables 4 4 and 4 5 ) . table 44 . pdata 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdata 15 C pdata 0 table 45 . pdata 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdata 31 C pdata16 bits [ 15 C 0 ] pdata15 C pdata0 pio data 0 bits this register contains the values of the bits that are either driven on, or received fr om, the corresponding pio pins. d epending on its configuration , each pin i s either an output or an input. the values of these bits correspond to those in the pio direction registers and pio mode registers. bits [ 15 C 0 ] pdata31 C pdata16 pio data 1 bits this register contains the values of the bits that are either driven on, or received f rom, the corresponding pio pins. depending on its configuration , each pin i s either an output or an input. the values of these bits correspond to those in the pio direction registers and pio mode registers the pio pins may be operated as open - drain outputs by: C maintaining th e data constant in the appropriate bit of the pio data register. C writing the value of the data bit into the respective bit position of the pio direction register, so that the output is either 0 or disabled depending on the value of the data bit.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 82 of 146 1 - 888 - 824 - 4184 5.1.27 pdir1 (078 h) and pdir0 (072h) p io dir ection registers. each pio pin is configured as an input or an output by the corresponding bit in the pio direction register (see table 4 6 ). table 46 . pio mode and pio direction settings pio mode pio d irection pin function 0 0 normal operation 0 1 pio input with pullup/pulldown 1 0 pio output 1 1 pio input without pullup/pulldown the value of the pdir0 register is fc0fh at reset (see table 4 7 ). table 47 . pdir0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir15 C pdir0 the value of the pdir1 register is ffffh at reset (see table 4 8 ). table 48 . pdir1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir 31 C pdir16 bits [ 15 C 0 ] pdir15 C pdir0 pio direction 0 bits fo r each bit, if the value is 1, th e pin is configured as an input. if 0 , as an output. the values of these bits correspond to those in the pio data registers and pio mode registers. bits [ 15 C 0 ] pdir31 C pdir16 pio direction 1 bits for each bit, if the val ue is 1, th e pin is configured as an input. if 0 , as an output. the values of these bits correspond to those in the pio data registers and pio mode registers. 5.1.28 p io mode1 (076h) and p io mode0 (070h) p io mode registers. each pio pin is configured as a pio or its normal function by the corresponding bit in the pio mode register. the bit number of pmod e corresponds to the pio number (s ee table 4 4 , pio mode and pio direction settings ) . the value of the piomode0 register is 0000h at reset (see table 4 9 ). table 49 . piomode0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pmode 15 C pmode 0
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 83 of 146 1 - 888 - 824 - 4184 the value of the piomode1 register is 0000h at reset (see table 50 ). table 50 . pmode1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pmode 31 C pmode16 bits [ 15 C 0 ] pmode15 C pmode0 pio mode 0 bits see table 46 . the values of these bits correspond to those in the pio data registers and pio mode registers. bits [ 15 C 0 ] pmode31 C pmode16 pio mode 1 bits see table 46 . the values of these bits correspond to those in the pio data registers and pio mode registers. 5.1.29 t1con (05eh) and t0con (056h) t ime r 0 and t ime r 1 mode and con trol registers. these registers control the operation of timer 0 and timer 1, respectively. the value of the t0con and t1con registers is 0000h at reset (see table 51 ). table 51 . t ime r 0 and t ime r 1 mode and con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en inhn int riu reserved mc rtg p ext alt cont bit [ 15 ] en enable bit the timer is enabled when the en bit is 1. the timer count is inhibited when the en bit is 0. this bit can only be written if the inhn bit (bit [14]) is set to 1 in the same operation. bit [ 14 ] inhn inhibit bit gates the setting of the enable ( en ) bi t. this bit must be set to 1 in the same write operation that changes the enable ( en ) bit. otherwise, the en bit will not be changed. this bit always reads 0. bit [ 13 ] int interrupt bit if set to 1, a n interrupt request is generated when the count re gister reaches its maximum, mc = 1. in dual maxcount mode, an interrupt request is generated when the count register reaches the value in maxcount a or maxcount b. no interrupt requests are generated if this bit is set to 0. if an interrupt request is g enerated , and the enable bit is then cleared before the interrupt is serviced, the interrupt request will remain. bit [ 12 ] riu register in use bit this bit is set to 1 when the maxcount register b is used to compare to the timer - count value. it is 0 when the maxcount compare a register is used. bits [ 11 C 6 ] reserved set to 0 .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 84 of 146 1 - 888 - 824 - 4184 bit [ 5 ] mc maximum count when the timer reaches its maximum count , this bit is set to 1 regardless of the interrupt enable bit. this bit is also set every time maxcount com pare register a or b is reached when in dual maxcount mode. if preferred, this bit may be used by software polling rather than by interrupts to monit or timer status . bit [ 4 ] rtg retrigger bit this pin controls the timer function of the timer input pin. when set to 1, the count is reset by a 0 to 1 transition on timrin0 or tmrin1. when 0, a high input on tmrin0 or tmrin1 enables the count and a 0 holds the timer value. this bit is ignored if the external clocking (ext = 1) bit is set. bit [ 3 ] p prescaler bit p is ignored if external clocking is enabled ( ext = 1). timer 2 prescales the timer when p is set to 1. otherwise, the timer is incremented on every fourth clkout cycle. bit [ 2 ] ext external clock bit this bit determines whether an external or internal clock is used. if ext is 1, an external clock is used. if 0, an internal is used. bit [ 1 ] alt alternate compare bit if set to 1, the timer will count to maxcount compare a, reset the count register to 0, count to maxcount compare b, reset the count register to 0 , and begin again at maxcount compare a. if 0, it will count to maxcount compare a, reset the count register to 0, and begin again at maxcount compare a. maxcount compare b is not used in this case. bit [ 0 ] cont continuous mode bit when set to 1, the timer run s continuously. when 0, the timer stop s after each count run and en will be cleared. if cont = 0 and alt = 1, the respective timer counts to the maxcount compare a value and resets, then commences counting to maxcount compar e b value, resets , and stops counting. 5.1.30 t2con (066h) t ime r 2 mode and con trol register. this register controls the operation of timer 2. the value of the t2con register is 0000h at reset (see table 5 2 ). table 52 . t ime r 2 mode and con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en inhn int reserved mc reserved cont bit [ 15 ] en enable bit the timer is enabled when the en bit is 1. the timer count is inhibited when the en bit is 0. modifying this bit by writing to the t2con register requires that the inh bit be s et to 1 during the same write. bit [ 14 ] inh n inhibit bit gates the setting of the enable ( en ) bit. this bit must be set to 1 in the same write operation that sets the enable ( en ) bit. this bit always reads 0.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 85 of 146 1 - 888 - 824 - 4184 bit [ 13 ] int interrupt bit an interrupt request is generated, by setting the int bit to 1, when the count register re aches its maximum, mc = 1. bits [ 12 C 6 ] reserved set to 0 . bit [ 5 ] mc maximum count when the timer reaches its maximum count , this bit is set to 1, regardless of the interrupt enable bit. if preferred, this bit may be used by software polling rather than by interrupts to monitor timer status. bits [4 C 1 ] reser ved set to 0. bit [ 0 ] cont continuous mode bit the timer will run continuously when this bit is set to 1. the timer will stop after each count run and en will be cleared if this bit is set to 0. 5.1.31 t2compa (062h) , t1compb (05ch) , t1compa (05ah) , t0compb (054h) , and t0compa (052h) t ime r maxcount com pare registers. these registers contain the maximum count value that is compared to the respec tive count register. timer 0 and timer 1 each have two compare registers. if timer 0 and/or timer 1 is/are configured to count and compare first to register a and then register b, the tmrout0 or tmrout1 signals can be used to generate various duty - cycle wave forms. timer 2 has only one compare register, t2co mpa. if one of these timer maxcount compare registers is set to 0000h, the respective timer will count from 0000h to ffffh before generating an interrupt request. for example, a timer configured in this manner with a 40 - mhz clock will interrupt every 6.55 36 ms. the value of these registers is undefined at reset (see table 5 3 ). table 53 . t ime r maxcount com pare registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0 bits [ 15 C 0 ] tc 15 C tc 0 timer compare value the timer will count to the value in the respective register before resetting the count value to 0.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 86 of 146 1 - 888 - 824 - 4184 5.1.32 t2cnt (060h) , t1cnt (058h) , and t0cnt (050h) these registers are incremented by one every four internal clock cycles if the relevant timer is enabled. t he increment of timer 0 and timer 1 may also be controlled by external signals tmrin0 and tmrin1 respectively, or prescaled by timer 2. comparisons are made between the count registers and maxcount registers and action taken dependent on achieving the maxi mum count. the value of these registers is undefined at reset (see table 5 4 ). table 54 . t imer c ou nt registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0 bits [ 15 C 0 ] tc 15 C tc 0 timer count value this register has the value of the current count of the related timer that is incremented every fourth processor clock in internal clocked mode. alternatively, the register is incremented each time the timer 2 maxcount is reached if using timer 2 as a p rescaler. timer 0 and timer 1 may be externally clocked by tmrin0 and tmrin1 signals. 5.1.33 spi con (044h) (master mode) s erial p ort i nterrupt c on trol register. this register controls the operation of the asynchronous serial port interrupt source (spi, bit [ 10 ] in the interrupt request register) . the value of this register is 001fh at reset (see table 5 5 ). table 55 . s erial p ort interrupt con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved msk pr2 C pr0 bits [ 15 C 5 ] reserved set to 0. bit [ 4 ] reserved set to 1. bit [ 3 ] msk mask this bit, when 0, enables the serial port to cause an interrupt. when this bit is 1, the serial port is prevented from generating an interrupt. bits [ 2 C 0 ] pr 2 C pr 0 priority these bits define the priority of the serial port interrupt in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown below.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 87 of 146 1 - 888 - 824 - 4184 values of pr2 C pr0 by priority priority pr2 C 5.1.34 wdcon (04 2 h) ( master mode ) watchdog timer interrupt c on trol register. these registers control the operation of the watchdog timer interrupt source. the value of this register is 000fh at reset (see tab le 56 ). table 56 . watchdog timer interrupt con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved res erved msk pr2 C pr0 bits [15 C 5] reserved set to 0. bit [4] reserved set to 0. bit [ 3 ] msk mask this bit, when 0, enables the watchdog timer to cause an interrupt. when this bit is 1 prevents the watchdog timer from generating an interrupt. bits [2 C 0 ] pr2 C pr0 priority these bits define the priority of the watchdog timer interrupt in relation to other interrupt sign als. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown in the above table . 5.1.35 i4con (040h) (master mode) this register controls the operation of the int4 signal, which is only in tended for use in fully nested mode. the interrupt is assigned to type 10h. the value of the i4con register is 000fh at reset (see table 5 7 ). table 57 . i nt 4 con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm ms k pr2 C pr0
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 88 of 146 1 - 888 - 824 - 4184 bits [ 15 C 5 ] reserved set to 0. bit [ 4 ] ltm level - triggered mode the int4 interrupt may be edge - or level - triggered, depending on the value of the bit. if ltm is 1, int4 is active high level - sensitive interrupt. if 0, it is a rising - edge t riggered interrupt. the interrupt int4 must remain active (high) until serviced. bit [ 3 ] msk mask the int4 signal can cause an interrupt if the msk bit is 0. the int4 signal cannot cause an interrupt if the msk bit is 1. bit s [2 C 0 ] pr 2 C pr 0 priority t hese bits define the priority of the interrupt in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown in the abov e table . 5.1.36 i3con (03eh) and i2con (03ch) (master mode) i nt 2 / i nt 3 con trol register. the int2 and int3 are designated as interrupt type 0eh and 0fh , respectively , and may be configured as the interrupt acknowledge pins inta0_n and inta1_n in cascade mode. the value of these register s is 000fh at reset (see table 5 8 ). table 58 . i nt 2 / i nt 3 con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm msk pr2 C pr0 bits [ 15 C 5 ] reserved set to 0. bit [ 4 ] ltm level - triggered mode the int2 or int3 interr upt may be edge - or level - triggered depending on the value of this bit. if ltm is 1, int2 or int3 is an active high level - sensitive interrupt. if 0, int2 or int3 is a rising - edge - triggered interrupt. the interrupt int2 or int3 must remain active (high) until acknowledged. bit [ 3 ] msk mask the int2 or int3 signal can cause an interrupt if the msk bit is 0. the int2 or int3 signal cannot cause an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bit s [ 2 C 0 ] pr 2 C pr 0 priority these bits define the prio rity of the interrupt int2 or int3 in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above . 5.1.37 i1con (03ah) and i0con (038h) (master mode) i nt 0 / i nt 1 con trol register. the int0 and int1 are designated as interrupt type 0ch and 0dh , respectively, and may be configured to use the interrupt acknowledge pins inta0 and inta1 in cascade mode. the value of these registers is 000fh at reset (see t able 5 9 ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 89 of 146 1 - 888 - 824 - 4184 table 59 . i nt 0 / i nt 1 con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sfnm c ltm msk pr2 C pr0 bits [ 15 C 7 ] reserved set to 0. bit [ 6 ] sf nm special fully nested mode this bit enables fully nested mode f or int0 or int1 when set to 1. bit [ 5 ] c cascade mode this bit enables cascade mo de for int0 or int1 when set to 1. bit [ 4 ] ltm level - triggered mode the int0 or int1 interrupt may be edge - or level - triggered depending on the value of the b it. if ltm is 1, int0 or int1 is an active high - level - sensitive interrupt. if 0, either is a rising - edge - triggered interrupt and must remain active ( high) until acknowledged. bit [ 3 ] msk mask the int0 or int1 signal can cause an interrupt if the msk bit is 0. if it is 1, they cannot. the interrupt mask register has a duplicate of this bit. bit s [ 2 C 0 ] pr 2 C pr 0 priority these bits define the priority of the int0 or int1 in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. t he values of pr2 C pr0 are shown above . 5.1.38 tcucon (032h) (master mode) t imer c ontrol u nit interrupt con trol register. the three timers have their interrupts assigned to types 08h, 12h, and 13h and are configured by this register. the value of this register is 000fh at reset (see table 60 ). table 60 . t imer c ontrol u nit interrupt con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 bits [ 15 C 4 ] reserved set to 0. bit [ 3 ] msk mask an interrupt source may cause an interrupt if the msk bit is 0. if 1, it cannot. the interrupt mask register has a duplicate of this bit. bit s [ 2 C 0 ] pr 2 C pr 0 priority these bits define the priority of the timer interrupt i n relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above .
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 90 of 146 1 - 888 - 824 - 4184 5.1.39 t2intcon (03ah) , t1intcon (038h) , and t0intcon (032h) (slave mode) t imer int er rupt con trol register. the three timers, timer 2, timer 1, and timer 0, each have an interrupt control register, whereas in master mode all three are masked and prioritized in one register (tcucon). the value of these registers is 000fh at reset (see tab le 61 ). table 61 . t imer int errupt con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 bits [ 15 C 4 ] reserved s et to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bi t is 0. if 1, they cannot. the interrupt mask register has a duplicate of this bit. bit s [ 2 C 0 ] pr 2 C pr0 priority these bits define the priority of the timer interrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above . 5.1.40 dma1con (036h) and dma0con (034h) (master mode) dma con trol register. the dma0 and dma1 interrupts have interrupt type 0ah and 0bh , respectively. the value of the se registers is 000fh at reset (see table 6 2 ). table 62 . dma int errupt con trol register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 bits [15 C 4 ] reserved set to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. if 1, they cannot . the interrupt mask register has a duplicate of this bit. bits [ 2 C 0 ] pr 2 C pr 0 priority these bits define the priority of the dma in terrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above . 5.1.41 dma1con (036h) and dma0con (034h) (slave mode) dma con trol register . the two dma control registers maintain their original functions and addressing that they possessed in master mode. the value of these registers is 000fh at reset (see table 6 3 ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 91 of 146 1 - 888 - 824 - 4184 table 63 . dma and int errupt con trol register (slav e mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 bits [ 15 C 4 ] reserved set to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. if 1, they cannot . the interrupt mask register has a duplic ate of this bit. bits [ 2 C 0 ] pr 2 C pr 0 priority these bits define the priority of the dma interrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above . 5.1.42 intsts (030h) (master mode) int errupt st atu s register . the interrupt status register contains the interrupt request status of each of the three timers, timer 2, timer 1, and timer 0 (see table 6 4 ). table 64 . int errupt st atu s register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt reserved tmr2 C tmr0 bit [ 15 ] dhlt dma halt dma activity is halted when this bit is 1. it is set to 1 automatically when any non - maskable interrupt occurs and is cleared to 0 when an iret instruction is executed. in terrupt handlers and other time - critical software may modify this bit directly to disable dma transfers. however, the dhlt bit should not be modified by software if the timer interrupts are enabled as the function of this register because an interrupt request register for the timers would be compromised. bits [ 14 C 3 ] reserved. bit s [ 2 C 0 ] t mr 2 C tmr 0 timer interrupt request a pending interrupt request is indicated by the corresponding timer, when any of these bits is 1. note: the tmr bit in the reqst register is a logical or of these timer interrupt requests. 5.1.43 intsts (030h) (slave mode) when nonmaskable interrupts occur , the interrupt status register controls dma operation and the interrupt request status of each of the three timers, timer 2, timer 1, and timer 0 (see table 6 5 ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 92 of 146 1 - 888 - 824 - 4184 table 65 . int errupt st atu s register ( slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt reserved tmr2 C tmr0 bit [ 15 ] dhlt dma halt dma activity is halted when this bit is 1. it is set to 1 automatically when any non - maskable interrupt occurs and is cleared to 0 when an iret instruction is executed. bits [ 14 C 3 ] reserved. bit s [ 2 C 0 ] tm r 2 C tmr 0 timer interrupt request a pending int errupt request is indicated by the corresponding timer, when any of these bits is 1. note: the tmr bit in the reqst register is a logical or of these timer interrupt requests. 5.1.44 reqst (02eh) (master mode) interrupt req ue st register. this is a read - only r egister and such a read results in the status of the interrupt request bits presented to the interrupt controller. the reqst register is undefined on reset (see table 6 6 ). table 66 . interrupt req ue st register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sp i wd i4 C i 0 d1 C d0 res erved tmr bits [ 15 C 11 ] reserved. bit [ 10 ] sp i serial port interrupt request this is the serial port interrupt state and when enabled is the logical or of all the serial p ort 0 interrupt so urces, thre, rdr, brki, fer, per, and oer. bit [9] wd watchdog timer interrupt request when it is a 1, the watchdog interrupt state indicates that an interrupt is pending. bits [ 8 C 4 ] i 4 C i 0 interrupt requests when set to 1 indicates that the relevant in terrupt has a pending interrupt. bit s [ 3 C 2 ] d1 C d0 dma channel interrupt request when set to 1 indicates that the respective dma channel has a pending interrupt. bit [1] reserved.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 93 of 146 1 - 888 - 824 - 4184 bit [ 0 ] tmr timer interrupt request this is the timer interrupt state a nd is the logical or of the timer interrupt requests. when set to 1 indicates that the timer control unit has a pending interrupt. 5.1.45 reqst (02eh) (slave mode) this is a read - only register and such a read results in the status of the interrupt request bits presente d to the interrupt controller. when an internal interrupt request ( d1, d0, tmr2, tmr1 , or tmr0 ) occurs, the respective bit is set to 1. the internally generated interrupt acknowledge resets these bits. the reqst register contains 0000h on reset (see table 6 7 ). table 67 . interrupt req ue st register (slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 C d0 res erved tmr0 bits [ 15 C 6 ] reserved. bit [ 5 ] tmr2 interrupt requests when set to 1 indicates tha t timer 2 has a pending interrupt. bit [ 4 ] tmr1 interrupt requests when set to 1 indicates that timer 1 has a pending interrupt. bit s [ 3 C 2] d1 C d0 dma channel interrupt request when set to 1 indicates that the respective dma channel has a pending interr upt. bit [ 1 ] reserved. bit [ 0 ] tmr0 timer interrupt request when set to 1 indicates that timer 0 has a pending interrupt. 5.1.46 inserv (02ch) (master mode) in - serv ice register. the interrupt controller sets the bits in this register when the interrupt is tak en. writing the corresponding interrupt type to the end - of - interrupt (eoi) register clears each of these bits. when one of these bits is set, an interrupt request will not be generated by the microcontroller for the respective source. this prevents an in terrupt from interrupting itself if interrupts are enabled in the isr. this restriction is bypassed in special fully nested mode for the int0 and int1 sources. the inserv register contains 0000h on reset (see table 6 8 ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 94 of 146 1 - 888 - 824 - 4184 table 68 . in - serv ice register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved spi wd i4 C i0 d1 C d0 res erved tmr bits [ 15 C 11 ] reserved. bit [ 10 ] spi serial port interrupt request this is the serial port 0 interrupt state. bit [9] wd watchdog timer i nterrupt in - service request this bit is the in - service state of the watchdog timer. bits [ 8 C 4 ] i 4 C i 0 interrupt requests these bit indicate that the corresponding interrupt has a pending interrupt. bit s [ 3 C 2] d1 C d0 dma channel interrupt in - service th is bit is the in - service state of the respective dma channel. bit [ 1 ] reserved. bit [ 0 ] tmr timer interrupt request this is the timer interrupt state and is the logical or of the timer interrupt requests. when set to 1 indicates that the timer control u nit has a pending interrupt. 5.1.47 inserv (02ch) (slave mode) this is a read - only register and such a read supplies the status of the interrupt request bits presented to the interrupt controller. when an internal interrupt request ( d1, d0, tmr2, tmr1 , and tmr0 ) is serviced , the respective bit is set to 1. the in - service bits are reset by writing to the eoi register . the inserv register contains 0000h on reset (see table 6 9 ). table 69 . in - serv ice register ( slave mode) 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 C d0 res erved tmr0 bits [ 15 C 6 ] reserved. bit [ 5 ] tmr2 timer 2 interrupt in service timer 2 is being serviced when this bit is set to 1. bit [ 4 ] tmr1 timer 1 interrupt in service timer 1 is being serviced whe n this bit is set to 1.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 95 of 146 1 - 888 - 824 - 4184 bit s [3 C 2] d1 C d0 dma channel interrupt in service the respective dma channel is being serviced when this bit is set to 1. bit [ 1 ] reserved. bit [ 0 ] tmr0 timer interrupt in service timer 0 is being serviced when this bit is set to 1. 5.1.48 primsk (02ah) (master and slave mode) pri ority m a sk register . this register contains a value that sets the minimum priority level at which an interrupt can be generated by a maskable interrupt. the primsk register contains 0007h on reset (see tab le 70 ). table 70 . pri ority m a sk register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved prm2 C prm0 bits [ 15 C 3 ] reserved set to 0. bits [ 2 C 0 ] prm 2 C prm 0 priority field mask this three - bit field sets the minimum priority necessary for a maskable interrupt to generate an interrupt. any maskable interrupt with a numerically higher value than that contained by these three bi ts is masked. the values of pr2 C pr0 are shown below. values of pr2 C pr0 by priority priority pr2 C any unmasked interrupt can generate an interrupt if the priority level is se t to 7. on the other hand, if the priority level is set to 4, only unmasked interrupts with a priority of 0 to 4 are permitted to generate interrupts. 5.1.49 imask (028h) ( master mode) interrupt mask register. the interrupt mask register is read/write. setting a bit in this register sets the msk bit in the corresponding interrupt control register. setting a bit to 1 masks the
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 96 of 146 1 - 888 - 824 - 4184 interrupt. the interrupt request is enabled when the corresponding bit is set to 0. the imask register contains 07fdh on reset (see ta ble 71 ). table 71 . i nterrupt mask register ( master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved spi wd i4 C i0 d1 C d0 res erved tmr bits [15 C 11] reserved. bit [10] spi serial port interrupt mask setting this bit to 1 indicates that the asynchronous serial port interrupt is masked. bit [9] wd watchdog timer interrupt in - service request setting this bit to 1 indicates that the watchdog timer interrupt is masked. bits [8 C 4] i 4 C i 0 interrupt mask setting any of these bits to 1 indicates that the relevant interrupt is masked. bit s [3 C 2] d1 C d0 dma channel interrupt mask setting this bit to 1 indicates that the respective dma channel interrupt is masked. bit [1] reserved. bit [0] tmr timer interr upt mask when set to 1 , it indicates that the timer control unit interrupt is masked. 5.1.50 imask (028h) (slave mode) interrupt mask register. the interrupt mask register is read/write. setting a bit in this register sets the msk bit in the corresponding in terrupt control register. setting a bit to 1 masks the interrupt request. the interrupt request is enabled when the corresponding bit is set to 0. the imask register contains 003dh on reset (see table 7 2 ). table 72 . i nterrupt m ask register (slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 C d0 res erved tmr0 bits [15 C 6] reserved. bit [5] tmr2 timer 2 interrupt mask this bit indicates the state of the mask bit in the timer interrupt control register. when set to 1, it indicates that the interrupt request is masked.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 97 of 146 1 - 888 - 824 - 4184 bit [4] tmr1 timer 1 interrupt mask this bit indicates the state of the mask bit in the timer inter rupt control register. when set to 1, it indicates that the interrupt request is masked. bit s [3 C 2] d1 C d0 dma channel interrupt mask this bit indicates the state of the mask bit in the respective dma channel interrupt control register. when set to 1, i t indicates that the interrupt request is masked. bit [1] reserved. bit [0] tmr0 timer interrupt mask this bit indicates the state of the mask bit in the timer interrupt control register. when set to 1, it indicates that the interrupt request is masked. 5.1.51 pollst (026h) (master mode) poll st atus register. this register reflects the current state of the poll register and can be read without affecting its contents. however, when the poll register is read, it causes the current interrupt to be acknowledged a nd replaced by the next interrupt. the poll status register is read - only (see table 7 3 ). table 73 . poll st atus reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq reserved s4 C s0 bit [ 15 ] ireq interrupt request this bit is set to 1 when an interrupt is pending. d uring this state the s4 C s0 bits contain valid data. bits [ 14 C 5] reserved. bit s [4 C 0 ] s 4 C s 0 poll status these bits show the interrupt type of the highest priority pending interrupt. the interrupt serv ice routine does not begin execution automatically with the is bit set. rather, the application software must execute the appropriate isr. 5.1.52 poll (024h) (master mode) poll register. when the poll register is read, it causes the current interrupt to be ackn owledged and be replaced by the next interrupt. the poll status register reflects the current state of the poll register and can be read without affecting its contents. the poll register is read - only (see table 7 4 ).
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 98 of 146 1 - 888 - 824 - 4184 table 74 . po ll register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq reserved s4 C s0 bit [ 15 ] ireq interrupt request this bit is set to 1 when an interrupt is pending. d uring this state , the s4 C s0 bits contain valid data. bits [ 14 C 5 ] reserved. bit s [ 4 C 0 ] s 4 C s 0 poll status these bits show the interrupt type of the highest priority pending interrupt. 5.1.53 eoi (022h) e nd - o f - i nterrupt register (master mode) the in service flags of the in - service register are reset when a write is made to the eoi register. the interrupt se rvice routine (isr) should write to the eoi to reset the is bit in the in - service register for the interrupt before executing an iret instruction that ends an interrupt service routine. because it is most secure, the specific eoi reset is the preferred me thod for resetting the is bits. the eoi register is write - only (see table 7 5 ). table 75 . e nd - o f - i nterrupt register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nspec reserved s4 C s0 bit [ 15 ] nspeq non - specific eoi when set to 1, this bit is a non - specific eoi. when 0, it indicates the specific eoi. bits [ 14 C 5 ] reserved. bit s [4 C 0 ] s 4 C s 0 source interrupt type these bits show the interrupt type of the interrupt being handled . 5.1.54 eoi (022h) specific e nd - o f - i nterrupt register (slave mode) a write clears the specific in - service flag indicated by l2 - l0 . the eoi register is wr ite - only and undefined at reset (see table 7 6 ). table 76 . specific e nd - o f - i nterrupt register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved l2 C l0 bits [ 15 C 3 ] reserved write as 0.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 99 of 146 1 - 888 - 824 - 4184 bit s [2 C 0 ] l 2 C l 0 interrupt type the priority or the is (interrupt service) bit to be reset is encoded in these three bits. writing to these bits caused the issuance of an eoi for the interrupt type (see table 14, interrupt types ) . 5.1.55 intvec (020h) int errupt vec tor register (slave mode) the cpu shifts left 2 bits (multiplies by 4) an 8 - bit interrupt type, generated by the interrupt controller, to produce an offset into the interrupt vector table. the i ntvec register is undefined at reset (see table 7 7 ). table 77 . int errupt vec tor register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved t4 C t0 reserved bits [15 C 8] reserved read as 0. bits [7 C 3] t 4 C t 0 interrupt type these five bits contain the five most significant bits of the interrupt types used for the internal interrupt type. the least significant three bits of the interrupt type are supplied by the interrupt controller, as set by the priority level of the interrupt request. bits [2 C 0] reserved read as 0. 5.1.56 ssr (018h) s ynchronous s erial r eceive register. this register holds the serial data received on the ssi port. the value of the ssr register is undefined at reset (see table 7 8 ). table 78 . s ynchronous s erial r eceive register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sr7 - sr0 bits [15 C 8] reserved. bits [7 C 0] sr7 C sr 0 data received over the sdata pin. 5.1.57 ssd0 (016h) and ssd 1 (014h) s ynchronous s erial transmit registers. these registers hold the data to be transmitted by the ssi ports. the value of these registers is undefined at reset (see table 7 9 ). table 79 . s ynchronous s erial transmit register s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sd7 C sd0
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 100 of 146 1 - 888 - 824 - 4184 bits [15 C 8] reserved. bits [7 C 0] sd7 C sd 0 data to be transmitted over the sdata pin. 5.1.58 ssc (012h) s ynchronous s erial c ontrol register. this register controls the operation of the sden1 and sden0 outputs and the baud rate of the ssi port. the sden1 and sden0 outputs are held high when the respec tive bit is set to 1, but in the event that both de1 and de0 are set to 1 then only sden0 will be held high. the value of the ssr register is 0000h at reset (see table 80 ). table 80 . s ynchronous s erial control register s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sclkdiv reserved de1 de0 bits [15 C 6] reserved. bits [5 C 4] sclkdiv sclk divide these bits set the sclk frequency. sclk is the result of dividing the internal processor clock by 2, 4, 8, or 16 as shown below . sclkdiv sclk frequency divider 00b processor clock /2 01b processor clock/4 10b processor clock/8 11b processor clock/16 bits [3 C 2] reserved. bit [1] de1 sden1 the sden1 bit is held high when this bit is set to 1 and sden1 is held low when this bit is set to 0. bit [0] de0 sden0 the sden0 bit is held high when this bit is set to 1 and sden0 is held low when this bit i s set to 0. 5.1.59 sss (010h) s ynchronous s erial s tatus register . this is a read - only register that indicates the state of the ssi port. the value of the ssr register is 0000h at reset (see table 81 ). table 81 . s ynchronous s erial stat us register s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved re/te dr/dt pb
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 101 of 146 1 - 888 - 824 - 4184 bits [15 C 3] reserved. bit [2] re/te receive/transmit error detect this bit is set to 1 when a read of the synchronous serial received register or a write to one of the transmit register is detected while the interface is busy (pb = 1). this bit is reset to 0 when the sden output is not active (de1 C de0 in the ssc regis ter are 00h). bit [1] dr/dt data receive/transmit complete this bit is set to a 1 when the transmission of data bit [ 7 ] is completed (sclk rising edge) during a transmit or receive operation. this bit is reset by a read of the ssr register, when either the ssd0 or ssd1 register is written, when the sss register is read (unless the ssi completes an operation and sets the bit in the same cycle), or when both sden0 and sden1 become inactive. bit [0] pb ssi port busy this bit indicates that a data transmi t or receive is occurring when it is set to 1. when set to 0 , it indicates that the port is ready to transmit or receive data. 5.2 reference documents additional information on the operatio n and programming of the ia 186er / ia 188er can be found in the followin g advanced micro devices ( amd ) publications: am186 er and am188 er microcontrollers users manual , march 1998 , publication 21684, rev b, amendment/1 . am186 er and am188 er data sheet , june 2000 , publication 20732 , rev . d , amendment 0. 6. ac specifications table 82 p rese nt s the ac characteristics over industrial operating ranges ( 50 mhz). tables 8 3 and 8 4 present the alphabetic and num eric keys to waveform parameters, respectively. figure 1 1 presents the read cycle. figure 1 2 presents the multiple read cycles. t able 8 5 presents the read cycle timing. figure 13 presents the write cycle. figure 14 presents the multiple write cycles. tab le 8 6 presents the write cycle timing. figure 15 presents the psram read cycle. table 8 7 presents the psram read cycle timing. figure 16 presents the psram write cycle. table 8 8 presents the psram write cycle timing. figure 17 presents the psram refresh cycle. table 8 9 presents the psram refresh cycle timing. figure 18 presents the interrupt acknowledge cycle. table 90 presen ts the interrupt acknowledge cycle timing. figure 19 presents the software halt cycle. table 91 presents the software halt cycle timing. figure 20 presents the clock active mode. figure 21 presents the clock power - save mode. table 92 presents the clock timing.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 102 of 146 1 - 888 - 824 - 4184 figure 22 presents the srdy synchronous ready. figure 23 presents the ardy asynchronous ready. figure 24 presents the peripheral s. table 93 presents the ready and peripheral timing. figures 25 and 26 present reset 1 and reset 2, respectively. figure s 27 and 28 present the bus hold entering and bus hold leaving, respectively. table 94 presents the reset and bus hold timing. figure 29 presents the synchronous serial interface. table 95 presents the synchronous serial interface timing. table 82 . ac characteristics over industrial operating ranges ( 5 0 mhz) no. name description min a max a general timing requirements 1 tdvcl data in setup 6.6 C 2 tcldx data in hold 2 C general timing responses 3 tchsv status active delay 0 10 4 tclsh status inacti ve delay 0 10 5 tclav ad address valid delay 0 10 6 tclax address hold 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 10 12 tavll ad address valid to ale low tclch C 13 tll ax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 15 tclaz ad address float delay 0 15 16 tclcsv mcs_n/pcs_n inactive delay 0 10 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tchcsx mcs_n/pcs_n inac tive delay 0 10 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 14 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 80 tclclx lcs_n inactive delay 0 10 81 tclcsl lcs_n active delay 0 10 82 tclrf clkouta high to rfsh_n invalid 0 10 84 tlrll lcs_n precharge pulse width tclcl + tclch C a all values are in nanoseconds, except where otherwise indicated.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 103 of 146 1 - 888 - 824 - 4184 table 8 2 . ac characteristics over industrial operating ranges ( 5 0 mhz) (continued) no. name description min a max a read cycle timing responses 24 tazrl ad address float to rd_n active 0 C 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width tclcl C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n inac tive to ale high tclch C 29 trhav rd_n inactive to ad address active tclcl C 30 tcldox data hold time 0 C write cycle timing responses 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 2tclcl C 33 twhlh wr_n inactive to ale high tclch C 34 twhdx data hold after wr_n tclcl C 35 twhdex wr_n inactive to den_n inactive tclch C 41 tdshlh ds_n inactive to ale inactive tclch C 59 trhdx rd_n high to data hold on ad bus 0 C 65 tavwl a address valid to wr_n low tclcl + tchcl C 66 tavrl a add ress valid to rd_n low tclcl + tchcl C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 10 68 tchav clkouta high to a address valid 0 10 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1.5 tchcl refresh timing cycle parameters 79 tchrfd clkouta high t o rfsh_n valid 0 12 82 tclrf clkouta high to rfsh_n invalid 0 12 85 trfcy rfsh_n cycle time 6tclcl C 86 tlcrf lcs_n inactive to rfsh_n active delay 2tclcl C clkin timing (times four mode) 36 tckin x1 period 80 125 37 tclck x1 low time 35 C 38 tchck x1 high time 35 C 39 tckhl x1 fall time C 5 40 tcklh x1 rise time C 5 clkout timing (times four mode) 42 tclcl clkouta period 20 C 43 tclch clkouta low time 9 C 44 tchcl clkouta high time 9 C 45 tch1ch2 clkouta rise time C 3 46 tcl2cl1 clkouta fall time C 3 61 tlock maximum pll lock time C 1 ms 69 tcicoa x1 to clkouta skew C 15 70 tcicob x1 to clkoutb skew C 21
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 104 of 146 1 - 888 - 824 - 4184 table 8 2 . ac characteristics over industrial operating ranges ( 5 0 mhz) (continued) no. name description min a max a ready and periphera l timing requirements 47 tsrycl srdy transition setup time 5 C 48 tclsry srdy transition hold time 2 C 49 tarych ardy resolution transition setup time 5 C 50 tclarx ardy active hold time 3 C 51 tarychl ardy inactive holding time 5 C 52 tarylcl ardy s etup time 5 C 53 tinvch peripheral setup time 5 C 54 tinvcl drq setup time 5 C peripheral timing responses 55 tcltmv timer output delay 0 10 reset & hold timing requirements 57 tresin res_n setup time 10 C 58 thvcl hld setup time 10 C reset and hold timing responses 62 tclhav hlda valid delay 0 10 63 tchcz command lines float delay 0 10 64 tchcv command lines valid delay (after float) 0 10 synchronous serial port timing requirements 75 tdvsh data valid to sclk high 10 C 77 tshdx sclk high to spi data hold 3 C synchronous serial port timing responses 71 tclev clkouta low to sden valid 0 10 72 tclsl clkouta low to sclk high 0 10 78 tsldv sclk low to data valid 0 10
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 105 of 146 1 - 888 - 824 - 4184 table 83 . alphabetic key to waveform parameter s no. name description 49 tarych ardy resolution transition setup time 51 tarychl ardy inactive holding time 52 tarylcl ardy setup time 87 tavbl a address valid to whb_n/wlb_n low 14 tavch ad address valid to clock high 12 tavll ad address valid to a le low 66 tavrl a address valid to rd_n low 65 tavwl a address valid to wr_n low 24 tazrl ad address float to rd_n active 45 tch1ch2 clkouta rise time 68 tchav clkouta high to a address valid 38 tchck x1 high time 44 tchcl clkouta high time 67 tchc sv clkouta high to lcs_n/usc_n valid 18 tchcsx mcs_n/pcs_n inactive delay 22 tchctv control active delay 2 64 tchcv command lines valid delay (after float) 63 tchcz command lines float delay 8 tchdx status hold time 9 tchlh ale active delay 11 tchll ale inactive delay 79 tchrfd clkouta high to rfsh_n valid 3 tchsv status active delay 69 tcicoa x1 to clkouta skew 70 tcicob x1 to clkoutb skew 39 tckhl x1 fall time 36 tckin x1 period 40 tcklh x1 rise time 46 tcl2cl1 clkouta fall time 50 tclarx ardy active hold time 5 tclav ad address valid delay 6 tclax address hold 15 tclaz ad address float delay 43 tclch clkouta low time 37 tclck x1 low time 42 tclcl clkouta period 80 tclclx lcs_n inactive delay 81 tclcsl lcs_n active delay 16 tclcsv mcs_n/pcs_n inactive delay 30 tcldox data hold time
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 106 of 146 1 - 888 - 824 - 4184 table 8 3 . alphabetic key to waveform parameters (continued) no. name description 7 tcldv data valid delay 2 tcldx data in hold 71 tclev clkouta low to sden valid 62 tclhav hlda valid delay 82 tcl rf clkouta high to rfsh_n invalid 27 tclrh rd_n inactive delay 25 tclrl rd_n active delay 4 tclsh status inactive delay 72 tclsl clkouta low to sclk low 48 tclsry srdy transition hold time 55 tcltmv timer output delay 83 tcoaob clkouta to clkoutb sk ew 20 tcvctv control active delay 1 31 tcvctx control inactive delay 21 tcvdex den_n inactive delay 17 tcxcsx mcs_n/pcs_n hold from command inactive 1 tdvcl data in setup 75 tdvsh data valid to sclk high 19 tdxdl den_n inactive to dt/ r_n low 58 thv cl hld setup time 53 tinvch peripheral setup time 54 tinvcl drq setup time 86 tlcrf lcs_n inactive to rfsh_n active delay 23 tlhav ale high to address valid 10 tlhll ale width 13 tllax ad address hold from ale inactive 61 tlock maximum pll lock time 84 tlrll lcs_n precharge pulse width 57 tresin res_n setup time 85 trfcy rfsh_n cycle time 29 trhav rd_n inactive to ad address active 59 trhdx rd_n high to data hold on ad bus 28 trhlh rd_n inactive to ale high 26 trlrh rd_n pulse width 77 tshdx sclk high to spi data hold 78 tsldv sclk low spi data hold 47 tsrycl srdy transition setup time 35 twhdex wr_n inactive to den_n inactive 34 twhdx data hold after wr_n 33 twhlh wr_n inactive to ale high 32 twlwh wr_n pulse width
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 107 of 146 1 - 888 - 824 - 4184 table 84 . numeric key to waveform parameters no. name description 1 tdvcl data in setup 2 tcldx data in hold 3 tchsv status active delay 4 tclsh status inactive delay 5 tclav ad address valid delay 6 tclax address hold 7 tcldv data valid delay 8 tchdx status hold time 9 tchlh ale active delay 10 tlhll ale width 11 tchll ale inactive delay 12 tavll ad address valid to ale low 13 tllax ad address hold from ale inactive 14 tavch ad address valid to clock high 15 tclaz ad address float dela y 16 tclcsv mcs_n/pcs_n inactive delay 17 tcxcsx mcs_n/pcs_n hold from command inactive 18 tchcsx mcs_n/pcs_n inactive delay 19 tdxdl den_n inactive to dt/ r_n low 20 tcvctv control active delay 1 21 tcvdex den_n inactive delay 22 tchctv control acti ve delay 2 23 tlhav ale high to address valid 24 tazrl ad address float to rd_n active 25 tclrl rd_n active delay 26 trlrh rd_n pulse width 27 tclrh rd_n inactive delay 28 trhlh rd_n inactive to ale high 29 trhav rd_n inactive to ad address active 30 tcldox data hold time 31 tcvctx control inactive delay 32 twlwh wr_n pulse width 33 twhlh wr_n inactive to ale high 34 twhdx data hold after wr_n 35 twhdex wr_n inactive to den_n inactive 36 tckin x1 period 37 tclck x1 low time 38 tchck x1 high time 39 tckhl x1 fall time 40 tcklh x1 rise time
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 8 of 146 1 - 888 - 824 - 4184 table 8 4 . numeric key to waveform parameters (continued) no. name description 42 tclcl clkouta period 43 tclch clkouta low time 44 tchcl clkouta high time 45 tch1ch2 clkouta rise time 46 tcl2cl1 cl kouta fall time 47 tsrycl srdy transition setup time 48 tclsry srdy transition hold time 49 tarych ardy resolution transition setup time 50 tclarx ardy active hold time 51 tarychl ardy inactive holding time 52 tarylcl ardy setup time 53 tinvch perip heral setup time 54 tinvcl drq setup time 55 tcltmv timer output delay 57 tresin res_n setup time 58 thvcl hld setup time 59 trhdx rd_n high to data hold on ad bus 61 tlock maximum pll lock time 62 tclhav hlda valid delay 63 tchcz command lines flo at delay 64 tchcv command lines valid delay (after float) 65 tavwl a address valid to wr_n low 66 tavrl a address valid to rd_n low 67 tchcsv clkouta high to lcs_n/usc_n valid 68 tchav clkouta high to a address valid 69 tcicoa x1 to clkouta skew 70 tcicob x1 to clkoutb skew 71 tclev clkouta low to sden valid 72 tclsl clkouta low to sclk high 75 tdvsh data valid to sclk high 77 tshdx sclk high to spi data hold 78 tsldv sclk low to data valid 79 tchrfd clkouta high to rfsh_n valid 80 tclclx lcs_ n inactive delay 81 tclcsl lcs_n active delay 82 tclrf clkouta high to rfsh_n invalid 83 tcoaob clkouta to clkoutb skew 84 tlrll lcs_n precharge pulse width 85 trfcy rfsh_n cycle time 86 tlcrf lcs_n inactive to rfsh_n active delay 87 tavbl a address valid to whb_n/wlb_n low
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 109 of 146 1 - 888 - 824 - 4184 figure 10 . read cycle ( ia186er ) ( ia186er ) ( ia18 8 er ) ( ia18 8 er ) c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) a o 1 5 C a o 8 ( i a 1 8 8 e m ) a l e r d _ n b h e _ n ( i a 1 8 6 e m ) l c s _ n , u c s _ n m c s _ n , p c s _ n d e n _ n / d s _ n d t / r _ n s 2 _ n C s 0 _ n u z i _ n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 110 of 146 1 - 888 - 824 - 4184 figure 11 . multiple read cycles (ia186er) (ia188er) c l k o u t a a 1 9 C a 0 a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a o 1 5 C a o 8 ( i a 1 8 8 e m ) l c s _ n , u c s _ n m c s _ n , p c s _ n s 2 _ n C s 0 _ n a l e r d _ n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 111 of 146 1 - 888 - 824 - 4184 table 85 . read cycle timing no. name description min a max a general timing requ irements 1 tdvcl data in setup 6.6 C 2 tcldx data in hold 2 C general timing responses 3 tchsv status active delay 0 10 4 tclsh status inactive delay 0 10 5 tclav ad address valid delay 0 10 6 tclax address hold 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width tclc l - 5 C 11 tchll ale inactive delay 0 10 12 tavll ad address valid to ale low tclch C 13 tllax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 15 tclaz ad address float delay 0 15 16 tclcsv mcs_n/pcs_n inactive delay 0 10 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tchcsx mcs_n/pcs_n inactive delay 0 10 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex d en_n inactive delay 0 14 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 5 C read cycle timing responses 24 tazrl ad address float to rd_n active 0 C 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width tclcl C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n inactive to ale high tclch C 29 trhav rd_n inactive to ad address active tclcl - 5 C 66 tavrl a address valid to rd_n low 30 C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 10 68 tchav clkouta high to a address va lid 0 10 a in nanoseconds.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 112 of 146 1 - 888 - 824 - 4184 figure 12 . write cycle ( ia186er ) ( ia186er ) ( ia186er ) ( ia18 8 er ) ( ia18 8 er ) ( ia18 8 er ) c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) a o 1 5 C a o 8 ( i a 1 8 8 e m ) a l e w r _ n w h b _ n , w l b _ n ( i a 1 8 6 e m ) , w b _ n ( i a 1 8 8 e m ) b h e _ n ( i a 1 8 6 e m ) l c s _ n , u c s _ n m c s _ n , p c s _ n d e n _ n / d s _ n d t / r _ n s 2 _ n C s 0 _ n u z i _ n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 113 of 146 1 - 888 - 824 - 4184 figure 13 . multiple write cycles c l k o u t a a 1 9 C a 0 a d 1 5 C a d 0 a l e w r _ n l c s _ n , u c s _ n m c s _ n , p c s _ n s 2 _ n C s 0 _ n
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 114 of 146 1 - 888 - 824 - 4184 table 86 . write cycle timing no. name description min a max a general timing responses 3 tchsv status active delay 0 10 4 tclsh status inactive delay 0 10 5 tclav ad address valid delay 0 10 6 tclax address hold 0 10 7 tcldv data valid delay 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay 0 10 12 tavll ad address valid to ale low tclch C 13 tllax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 16 tclcsv mcs_n/pcs_n inactive delay 0 10 17 tcxcsx mcs_n/pcs_n hold fro m command inactive tclch C 18 tchcsx mcs_n/pcs_n inactive delay 0 10 19 tdxdl den_n inactive to dt/r_n low 0 C 20 tcvctv control active delay 1 0 10 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 5 C write cycle timing respo nses 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 35 C 33 twhlh wr_n inactive to ale high tclch - 2 C 34 twhdx data hold after wr_n tclcl C 35 twhdex wr_n inactive to den_n inactive 12 C 65 tavwl a addre ss valid to wr_n low tclcl + tchcl - 1.25 C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 10 68 tchav clkouta high to a address valid 0 10 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1. 2 5 C a in nanoseconds.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 115 of 146 1 - 888 - 824 - 4184 figure 14 . psram read cycle ( ia186er ) (ia188er) (ia188er) c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) a o 1 5 C a o 8 ( i a 1 8 8 e m ) a l e r d _ n l c s _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns c l k o u t a a 1 9 - a 0 s 6 / l o c k _ n a d 1 5 - a d 0 / a d 7 - a d 0 a o 1 5 - a o 8 a l e r d _ n l c s _ n address address s6 lock_n s6 s6 address data address address address 66 68 8 7 1 2 9 23 11 10 59 24 26 28 25 27 5 81 80 84
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 116 of 146 1 - 888 - 824 - 4184 table 87 . psram read cycle timing no. name comment min a max a general timing requirements 1 tdvcl data in setup 6.6 C 2 tcldx data in hold 2 C general timing responses 5 tclav ad address valid delay 0 1 0 7 tcldv data valid delay 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay 0 10 23 tlhav ale high to address valid 7.5 C 80 tclclx lcs_n inactive delay 0 10 81 tclcsl lcs_n active delay 0 10 84 tlrll lcs_n precharge pulse width tclcl+ tclch C read cycle timing responses 24 tazrl ad address float to rd_n active 0 C 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width 35 C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n in active to ale high tclch C 59 trhdx rd_n high to data hold on ad bus 0 C 66 tavrl a address valid to rd_n low 30 C 68 tchav clkouta high to a address valid 0 10 a in nanoseconds.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 117 of 146 1 - 888 - 824 - 4184 figure 15 . psram write cycle ( ia186er ) ( ia186er ) (ia188er) (ia188er) (ia188er) c l k o u t a a 1 9 C a 0 s 6 a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) a o 1 5 C a o 8 ( i a 1 8 8 e m ) a l e w r _ n l c s _ n w h b _ n , w l b _ n ( i a 1 8 6 e m ) , w b _ n ( i a 1 8 8 e m ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k o u t a a 1 9 - a 0 s 6 / l o c k _ n a d 1 5 - a d 0 / a d 7 - a d 0 a o 1 5 - a o 8 a l e w r _ n w h b _ n / w l b _ n / w b _ n l c s _ n address address s6 lock_n s6 s6 address data data address address 65 68 8 7 30 9 23 11 34 10 33 32 31 5 20 20 31 87 80 81 80 84
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 118 of 146 1 - 888 - 824 - 4184 table 88 . psram write cycle timing no. name comment min a max a general timing responses 5 tclav ad address valid delay 0 10 7 tcldv data valid delay 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay C 10 20 tcvctv control active delay 1 0 10 23 tlhav ale high to address valid 5 C 80 tclclx lcs_n inactive delay 0 10 81 tclcsl lcs_n active delay 0 10 84 tlrll lcs_n precharge pulse width tclcl+ tclch C write cycle timing responses 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 35 C 33 twhlh wr_n inactive to ale high tclch - 2 C 34 twhdx data hold after wr_n 12 C 65 tavwl a address valid to wr_n low tclcl+ tchcl - 1 C 68 tchav clkouta high to a address valid 0 10 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1 C a in nanoseconds.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 119 of 146 1 - 888 - 824 - 4184 figure 16 . psram refresh cycle table 89 . psram refresh cycle no. name comm ent min a max a general timing responses 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay 0 10 read/write cycle timing responses 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width 35 C 27 tclrh rd_n inactive de lay 0 10 28 trhlh rd_n inactive to ale high tclch - 2 C 80 tclclx lcs_n inactive delay 0 10 81 tclcsl lcs_n active delay 0 10 refresh cycle timing responses 79 tchrfd clkouta high to rfsh_n valid 0 10 82 tclrf clkouta high to rfsh_n invalid 0 10 85 t rfcy rfsh_n cycle time 6tclcl C 86 tlcrf lcs_n inactive to rfsh_n active delay 2tclcl - 1 C a in nanoseconds. c l k o u t a a 1 9 C a 0 a l e r d _ n l c s _ n r f s h _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k 0 a 1 9 - a 0 a l e r d _ n l c s _ n r f s h _ n address address 9 11 10 26 28 27 27 80 81 25 79 82 86 85
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 120 of 146 1 - 888 - 824 - 4184 figure 17 . internal ram show read cycle table 90 internal ram show read cycle (40 mhz and 50 mhz)
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 121 of 146 1 - 888 - 824 - 4184 figure 18 . interrupt acknowledge cycl e ( ia186er ) ( ia186er ) (ia188er) (ia188er) c l k o u t a a 1 9 C a 0 a l e b h e _ n ( i a 1 8 6 e m ) i n t a 1 _ n , i n t a 0 _ n a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) s 6 a o 1 5 C a o 8 ( i a 1 8 8 e m ) d e n _ n d t / r _ n s 1 _ n C s 0 _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clk0 a19 - a0 s6/lock_n ad15 - ad 0/ad7 - ad0 ao15 - ao8 ale bhe_n inta1_n/inta0_n den_n dt_r_n s2_n - s0_n address address s6 lock_n s6 s6 ptr address bhe_n bhe_n 68 7 8 12 1 2 9 23 15 10 11 4 31 20 22 19 22 22 21 3 4
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 122 of 146 1 - 888 - 824 - 4184 table 91 . interrupt acknowledge cycle timing no. name description min a max a general timing requirements 1 tdvcl data in setup 6.6 C 2 tcldx data in hold 2 C general timing responses 3 tchsv status active delay 0 10 4 tcl sh status inactive delay 0 10 7 tcldv data valid delay 0 10 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay 0 10 12 tavll ad address valid to ale low tclch C 15 tclaz ad address float de lay 0 10 19 tdxdl den_n inactive to dt/r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 10 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 5 C 31 tcvctx control inactive delay 0 10 68 tchav clkouta high to a address valid 0 10 a in nanoseconds.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 123 of 146 1 - 888 - 824 - 4184 figure 19 . software halt cycle table 92 . software halt cycle timing no. name description min a max a general timing responses 3 tchsv status active delay 0 10 4 tclsh status inactive delay 0 10 5 tclav ad address valid delay 0 10 9 tchlh ale active delay 0 10 10 tlhll ale width 15 C 11 tchll ale inactive delay 0 10 19 tdxdl den_n inactive to dt/r_n low 0 C 22 tchctv control active delay 2 0 10 68 tchav clkouta high to a address valid 0 10 a in nanoseconds. ( ia186er ) (ia188er) (ia188er) c l k o u t a a 1 9 C a 0 a l e a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a d 8 C a d 0 ( i a 1 8 8 e m ) , a o 1 5 C a o 8 ( i a 1 8 8 e m ) d e n _ n d t / r _ n s 1 _ n C s 0 _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k o u t a a 1 9 - a 0 s 6 / a d [ 1 5 : 0 / a d [ 8 : 0 ] / a o [ 1 5 : 8 ] a l e d e n _ n d t _ r _ n s 2 _ n - s 0 _ n invalid address invalid address invalid address invalid address status status 68 5 10 9 11 19 3 4 22
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 124 of 146 1 - 888 - 824 - 4184 figure 20 . clock active mode figure 21 . clock power - save mode c l k o u t a x 2 x 1 c l k o u t b 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x 2 x 1 c l k o u t a c l k o u t b 36 37 38 69 42 43 44 70 c l k o u t a x 2 x 1 c l k o u t b ( c b f = 1 ) c l k o u t b ( c b f = 0 ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x 2 x 1 c l k o u t a c l k o u t b ( c b f = 1 ) c l k o u t b ( c b f = 0 )
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 125 of 146 1 - 888 - 824 - 4184 table 93 . clock timing no. name d escription min max units clkin requirements (times four mode) 36 tckin x1 period 80 125 ns 37 tclck x1 low time 35 C ns 38 tchck x1 high time 35 C ns 39 tckhl x1 fall time C 5 ns 40 tcklh x1 rise time C 5 ns clkout timing 42 tclcl clkouta period 20 C ns 43 tclch clkouta low time 9 C ns 44 tchcl clkouta high time 9 C ns 45 tch1ch2 clkouta rise time C 3 ns 46 tcl2cl1 clkouta fall time C 3 ns 61 tlock maximum pll lock time C 1 ms 69 tcicoa x1 to clkouta skew C 15 ns 70 tcicob x1 to clkoutb skew C 21 ns a in nanoseconds. figure 22 . srdy synchronous ready c l k o u t a s r d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns c l k o u t a s r d y 47 48
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 126 of 146 1 - 888 - 824 - 4184 figure 23 . ardy asynchronous ready figure 24 . peripherals c l k o u t a a r d y a r d y a r d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns c l k o u t a a r d y a r d y a r d y sytem normally not ready sytem normally ready system normally ready 49 49 50 50 51 52 c l k o u t a i n t 4 C i n t 0 , n m i , t m r i n 1 C t m r i n 0 d r q 1 C d r q 0 t m r o u t 1 C t m r o u t 0 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns c l k o u t a i n t 4 - 0 / n m i / t m r i n 1 - 0 d r q 1 - d r q 0 t m r o u t 1 - t m r o u t 0 53 54 55
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 127 of 146 1 - 888 - 824 - 4184 table 94 . ready and peripheral timing no. name description min a max a ready and peripheral timing requirements 47 tsrycl srdy transition setup time 10 C 48 tclsry srdy transition hold time 3 C 49 tarych ardy resolution transition setup time 9 C 50 tclarx ardy active hold time 4 C 51 tarychl ardy inactive holding time 6 C 52 tarylcl ardy setup time 9 C 53 tinvch periphe ral setup time 10 C 54 tinvcl drq setup time 10 C peripheral timing responses 55 tcltmv timer output delay 0 12 a in nanoseconds. figure 25 . reset 1 figure 26 . reset 2 (ia186er) (ia188er) (ia188er) x 1 r e s _ n c l k o u t a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns x 1 r e s _ n c l k o u t a low for n x1 cycles 57 57 b h e _ n / a d e n _ n , r f s h _ n / a d e n _ n , s 6 / c l k d i v 2 , u z i _ n r e s _ n c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e m ) , a o 1 5 C a o 8 ( i a 1 8 8 e m ) , a d 7 C a d 0 ( i a 1 8 8 e m ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns r e s _ n c l k o u t a b h e _ n / a d e n _ n , r f s h 2 _ n / a d e n _ n / s 6 , u z i _ n a d [ 1 5 : 0 ] , a 0 [ 1 5 : 8 ] , a d [ 7 : 0 ] tri-state tri-state
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 128 of 146 1 - 888 - 824 - 4184 figure 27 . bus hold entering figure 28 . bus hold leaving (ia186er) (ia186er) (ia186er) (ia186er) (ia186er) (ia186er) (ia186er) (ia186er) a d 1 5 C a d 0 ( i a 1 8 6 e m ) , s 6 , r d _ n , w r _ n , b h e _ n ( i a 1 8 6 e m ) , d t / r _ n , s 2 _ n C s 1 _ n , w h b _ n , w l b _ n ( i a 1 8 6 e m ) h o l d c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e m ) , d e n _ n h l d a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 15 63 a d 1 5 C a d 0 ( i a 1 8 6 e m ) , s 6 , r d _ n , w r _ n , b h e _ n ( i a 1 8 6 e m ) , d t / r _ n , s 2 _ n C s 1 _ n , w h b _ n , w l b _ n ( i a 1 8 6 e m ) h o l d c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e m ) , d e n _ n h l d a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 5 64
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 129 of 146 1 - 888 - 824 - 4184 table 95 . reset and bus hold timing no. name description min a max a reset and bus hold timing requirements 5 tclav ad address valid delay 0 12 15 tclaz ad address float delay tclch C 57 tresin res_n setup time 10 C 58 thvcl hld setup time 10 C reset and bus hold timing responses 62 tclhav hlda valid delay 0 7 63 tchcz command lines float delay 0 12 64 tchcv command lines valid delay (after float) 0 12 a in nanoseconds. figure 29 . synchronous serial interface s d a t a ( t x ) s d e n c l k o u t a s d a t a ( r x ) s c l k 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta sden sclk sdata(rx) sdata(tx) 71 72 75 78 77 data data
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 130 of 146 1 - 888 - 824 - 4184 table 96 . synchronous serial interface timing no. name description min a max a synchronous serial port timing requirements 75 tdvsh data valid to sclk high 10 C 77 tshdx sclk high to spi data hold 3 C synchronous serial port timing responses 71 tclev clko uta low to sden valid 0 12 72 tclsl clkouta low to sclk low 0 12 78 tsldv sclk low to data valid 0 12 a in nanoseconds. 7. instruction set summary table table 9 7 summarizes each instruction. a key to abbreviations is presented at the end of the table. ta ble 97 . instruction set summary instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c aaa ascii adjust al after add 37 C C u C C C u u r u r aad ascii adjust ax before divide. d5 0a C u C C C r r u r u aam ascii adjust al after multiply d4 0a C u C C C r r u r u aas ascii adjust al after subtract 3f C C u C C C u u r u r adc add imm8 to al with carry 14 ib C r C C C r r r r r add imm16 to ax with carry 15 iw C add imm8 to r/m8 with carry 80 /2 ib add imm16 to r/m16 with carry 81 /2 iw add sign extended imm8 to r/m16 with carry 83 /2 ib add byte reg to r/m8 with carry 10 /r C add word reg to r/m16 with carry 11 /r C add r/m8 to byte reg with carry 12 /r C add r/m16 to word reg with carry 13 /r C add add imm8 to al 04 ib C r C C C r r r r r add imm16 to ax 05 iw C add imm8 to r/m8 80 /0 ib add imm16 to r/m16 81 /0 iw add sign extended imm8 to r/m16 83 /0 ib add byte reg. to r/m8 00 /r C add word reg. to r/m16 01 /r C add r/m8 to byte reg 02 /r C add r/m16 to word reg 03 /r C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 131 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set sum mary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c and and imm8 with al 24 ib 0 C C C r r u r 0 and imm16 with ax 25 iw and imm8 with r/m8 80 /4 ib and imm16 w ith r/m16 81 /4 iw and sign - extended imm8 with r/m16 83 /4 ib and byte reg. with r/m8 20 /r and word reg. with r/m16 21 /r and r/m8 with byte reg 22 /r and r/m16 with word reg 23 /r bound check array index against bounds 62 /r C C C C C C C C C C call call near, disp relative to next instruction e8 cw C C C C C C C C C C call near, reg indirect mem ff /2 C call far to full address given 9a cd C call far to address at m16:16 word ff /3 C cbw convert byte integer to word 98 C C C C C C C C C C C clc clear carry flag f8 C C C C C C C C C C 0 cld clear direction flag fc C C C 0 C C C C C C C cli clear interrupt - enable flag fa C C C C 0 C C C C C C cmc comp lement carry flag f5 C C C C C C C C C C r cmp compare imm8 to al 3c ib r C C C r r r r r compare imm16 to ax 3d iw C compare imm8 to r/m8 80 /7 ib compare imm16 to r/m16 81 /7 iw compare sign - extended imm8 to r/m16 83 /7 ib compare byte reg to r/m8 38 /r compare word reg to r/m16 39 /r C compare r/m8 to byte reg 3a /r C compare r/m16 to word reg 3b /r C cmps compare byte es:[di] to byte segment: [si] a6 C C r C C C r r r r r compare word es: [di] to word segment: [si] a7 C C cmpsb compare byte es:[di] to byte ds: [si] a6 C C r C C C r r r r r cmpsw compare word es:[di] to word ds: [si] a7 C C r C C C r r r r r cs cs segment reg override prefix 2e C C C C C C C C C C C cwd convert word integer to double word 99 C C C C C C C C C C C daa decimal adjust al after addition 27 C C u C C C r r r r r das decimal adjust al after subtraction 2f C C u C C C r r r r r dec subtract 1 from r/m8 fe /1 C r C C C r r r r r subtract 1 from r/m16 ff /1 C subtract 1 from word reg 48+rw div divide unsigned numbers f6 mod 110 r/m C u C C C u u u u u
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 132 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic descri ption byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c ds ds segment override prefix 3e C C C C C C C C C C C enter create stack frame for nested procedure c8 iw ib C C C C C C C C C create stack frame for non - nested procedure c8 iw 00 create stack frame for nested procedure c8 iw 01 es es segment reg override prefix 26 C C C C C C C C C C C esc escape - takes a trap 7 d8 /0 C C C 0 0 C C C C C escape - takes a trap 7 d9 /1 C escape - takes a trap 7 da /2 C escape - takes a trap 7 db /3 C escape - takes a trap 7 dc /4 C escape - takes a trap 7 dd /5 C escape - takes a trap 7 de /6 C escape - takes a trap 7 df /7 C hlt suspend instruction execution f4 C C C C C C C C C C C idiv divide integers al = ax/(r/m8); ah = remainder f6 /7 C u C C C u u u u u divide integers ax = dx: ax/(r/m16); dx = remainder f7 /7 C imul multiply integers ax=(r/m8)*al f6 /5 C r C C C u u u u r multiply integers dx=(r/m16)*ax f7 /5 C multiply integers (word reg) = (r/m16)*(sign - ext. byte integer) 6b /r ib multiply integers (word reg) = (word reg)*(sign - ext. byte integer) 6b /r ib multiply integers (word reg) = (r/m16)*(sign - ext. word integer) 69 /r iw multiply integers (word r eg) = (word reg)*(sign - ext. word integer) 69 /r iw in input byte from imm port to al e4 ib C C C C C C C C C C input word from imm port to ax e5 ib C input byte from port in dx to al ec C input word from port in dx to ax ed C inc increment r/m8 by 1 fe /0 C r C C C r r r r - increment r/m16 by 1 ff /0 C increment word reg by 1 40+rw C C ins input byte from port in dx to es : [di] 6c C C C C C C C C C C C i nput word from port in dx to es :[di] 6d insb input byte from port in dx to es :[di] 6c
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 133 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c insw input word from port in dx to es :[di] 6d int 3 generate interrupt 3 (trap to debug) cc C C C C 0 0 C C C C C int generate type of interrupt specified by imm8 cd ib C into generate interrupt 4 if overflow flag (o) is 1 ce C C iret interrupt return cf C C restores value of flags reg that was stored on the stack when the interrupt was taken . ja jump short if above ( c & z = 0) 77 cb C C C C C C C C C C jnbe jump short if not below or equal ja e jump short if above or equal ( c =0) 73 cb C C C C C C C C C C jnb jump short if not below ( c =0) jnc jump short if not carry ( c =0) jb jump short if below ( c =1) 72 cb C C C C C C C C C C jc jump short if carry ( c =1) jnae jump short if not above or equal ( c =1) jbe jump short if below or equal ( c & z = 0) 76 cb C C C C C C C C C C jna jump short if not above ( c & z = 0) jcxz jump short if cx reg is 0 e3 cb C C C C C C C C C C je jump short i f equal ( z =1) 74 cb C C C C C C C C C C jz jump short if 0 ( z =1) jg jump short if greater (z & s = o) 7f cb C C C C C C C C C C jnle jump short if not less or equal ( z & s = o) jge jump short if greater or equal ( s =o) 7d cb C C C C C C C C C C jnl jump short if not less (s = o) jl/jnge jump short if less (s o) 7c cb C C C C C C C C C C jle jump short if less or equal ( z or s = o) 7e cb C C C C C C C C C C jng jump short if not greater (z or s = o) jmp jump short direct, disp relative to next instruction eb cb C C C C C C C C C C jump near direct, disp relative to next instruction e9 cw C jump near indirect ff /4 C jump far direct to doubleword imm address ea cd C jump m16: 16 indirect and far ff /5 C jne jump short if not equal ( z =0) 75 cb C C C C C C C C C C jnz jump short if not zero ( z =0) jno jump short if not overflow (o=1) 71 cb C C C C C C C C C C jnp jump short if not parity ( p = 0) 7b cb C C C C C C C C C C jpo jump short if parity odd ( p =0) jns jump short if not sign ( s =0) 79 cb C C C C C C C C C C jo jump short if overflow ( o =1) 70 cb C C C C C C C C C C jp jump short if parity ( p =1) 7a cb C C C C C C C C C C jp e jump short if parity ( p =1)
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 134 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c js jump short if sign ( s =1) 78 cb C C C C C C C C C C lahf l oad ah with low byte of flags reg 9f C C C C C C C C C C C lds load ds:r16 with segment offset from memory c5 /r C C C C C C C C C C lea load offset for m16 word in 16 - bit reg 8d /r C C C C C C C C C C leave destroy procedure stack frame c9 C C C C C C C C C C C les load es:r16 with segment offset from memory c4 /r C C C C C C C C C C lock asserts lock_n during an instruction execution f0 C C C C C C C C C C C lods load byte segment : [si] in al ac C C C C C C C C C C C load word segment : [si] in ax ad lodsb load byte ds: [si] in al ac lodsw load word ds: [si] in ax ad loop decrement count ; jump short if cx 0 e2 C C C C C C C C C C C loope decrement count ; jump short if cx 0 and z = 1 e1 cb C loopz de crement count ; jump short if cx 0 and z = 1 loopne decrement count ; jump short if cx 0 and z = 0 e0 cb C C C C C C C C C C loopnz decrement count ; jump short if cx 0 and z = 0 mov copy reg to r/m8 88 /r C C C C C C C C C C copy reg to r/m16 89 /r C copy r/m8 to reg 8a /r C copy r/m16 to reg 8b /r C copy segment reg to r/m16 8c /sr C copy r/m16 to segment reg 8e /sr C copy byte at segment offset to al a0 C C copy word at segment offset to ax a1 C C copy al to byte at segment offset a2 C C copy ax to word at segment offset a3 C C copy imm8 to reg b0+rb C C copy imm16 to reg b8+rw copy imm8 to r/m8 c6 /0 C copy imm16 to r/m16 c7 /0 C movs copy byte segment [si] to es:[di] a4 C C C C C C C C C C C copy word segment [si] to es:[di] a5 C C movsb copy byte ds:[si] to es:[di] a4 C C movsw copy word ds:[si] to es:[d i] a5 C C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 135 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c mul ax = (r/m8) * al f6 /4 C r C C C C C C C r dx:: ax = (r/m16) * ax f7 /4 neg perform 2's complement negation of r/m8 f6 /3 C r C C C r r r r r perform 2's complement negation of r/m16 f7 /3 C nop perform no operation 90 C C C C C C C C C C C not complement each bit in r/m8 f6 /2 C C C C C C C C C C complemen t each bit in r/m16 f7 /2 or or imm8 with al 0c ib C 0 C C C r r u r 0 or imm16 with ax 0d iw or imm8 with r/m8 80 /1 ib or imm16 with r/m16 81 /1 iw or imm8 with r/m16 83 /1 ib or byte reg with r/m 8 08 /r C or word reg with r/m16 09 /r C or r/m8 with byte reg 0a /r C or r/m16 with word reg 0b /r C out output al to imm port e6 ib C C C C C C C C C C output ax to imm port e7 ib C output al to por t in dx ee C C output ax to port in dx ef C C outs output byte ds:[si] to port in dx 6e C C C C C C C C C C C output word ds:[si] to port in dx 6f C C outsb output byte ds:[si] to port in dx 6e C C outsw output wo rd ds:[si] to port in dx 6f C C pop pop top word of stack into memory word 8f /0 C C C C C C C C C C pop top word of stack into word reg 58+rw C C pop top word of stack into ds 1f C C pop top word of stack into es 07 C C pop top word of stack into ss 17 C C popa pop di, si, bp, bx, dx, cx, & ax 61 C C values in word at top of stack are copied into flags reg bits . popf pop top word of stack into processor status flags reg 9d C C push push memory wo rd onto stack ff /6 C C C C C C C C C C push reg word onto stack 50+rw C C push sign - extended imm8 onto stack 6a cb C push imm16 onto stack 68 cw C push cs onto stack 0e C C push ss onto stack 16 C C push ds onto stack 1e C C push es onto stack 06 C C pusha push ax, cx, dx, bx, original sp, bp, si, and di 60 C C C C C C C C C C C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 136 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic des cription byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c pushf push processor status flags reg 9c C C C C C C C C C C C rcl rotate 9 bits of c and r/m8 left once d0 /2 C u C C C C C C C r rotate 9 bits of c and r/m8 left cl times d2 /2 C rotate 9 bits of c and r/m8 left imm8 times c0 /2 ib rotate 17 bits of c and r/m16 left once d1 /2 C rotate 17 bits of c and r/m16 left cl times d3 /2 C rotate 17 bits of c and r/m16 left imm8 times c1 /2 ib rcr rotate 9 bits of c and r/m8 right once d0 /3 C u C C C C C C C r rotate 9 bits of c and r/m8 right cl times d2 /3 C rotate 9 bits of c and r/m8 right imm8 times c0 /3 ib C rotate 17 bits of c and r/m16 right once d1 /3 C rotate 17 bits of c and r/m16 right cl times d3 /3 C rotate 17 bits of c and r/m16 right imm8 times c1 /3 ib rep ins input cx bytes from port in d x to es: [di] f3 6c C C C C C C C C C C input cx bytes from port in dx to es: [di] f3 6d C rep lods load cx bytes from segment : [si] in al f3 ac C C C C C C C C C C load cx words from segment : [si] in ax f3 ad C rep movs copy cx bytes from segments : [si] to es:[di] f3 a4 C C C C C C C C C C copy cx words from segments : [si] to es:[di] f3 a5 C rep outs output cx bytes from ds:[si] to port in dx f3 6e C C C C C C C C C C output cx bytes from ds:[si] to port in dx f3 6f C rep stos fill cx bytes at es:[di] with al f3 aa C C C C C C C C C C fill cx words a t es:[di] with al f3 ab C repe cmps find non - matchi ng bytes in es:[di] and segment : [si] f3 a6 C C C C C C C C C C find non - matchi ng words in es:[di] and segment : [si] f3 a7 C repe scas find non - al byte starting at es:[di] f3 ae C find non - ax word starting at es:[di] f3 af C repz cmps find non - matching bytes in es:di and segment :[si] f3 a6 C find non - matching words in es:di and segment :[si] f3 a7 C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 137 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continu ed) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c repz scas find non - al byte starting at es:di f3 ae C find non - ax word starting at es:di f3 af C repne cmps find matching bytes in es:[di] and segment :[si] f2 a6 C C C C C C C C C C find matching words in es:[di] and segment :[si] f2 a7 C repnz cmps find al byte starting at es:[di] f2 a6 C find ax word starting at es:[di] f2 a7 C repne scas find m atching bytes in es:di and segment :[si] f2 ae C find matching words in es:di and segment :[si] f2 af C repnz scas find al byte starting at es:di f2 ae C find ax word starting at es:di f2 af C ret return near to ca lling procedure c3 C C C C C C C C C return far to calling procedure cb - - return near; pop imm16 parameters c2 data low data high return far; pop imm16 parameters ca data low data high rol rotate 8 bits of r/m8 left on ce d0 /0 C u C C C C C C C r rotate 8 bits or r/m8 left cl times d2 /0 C rotate 8 bits or r/m8 left imm8 times c0 /0 data 8 rotate 16 bits of r/m8 left once d1 /0 C rol rotate 16 bits or r/m8 left cl times d3 /0 C u C C C C C C C r rotate 16 bits or r/m8 left imm8 times c1 /0 data 8 ror rotate 8 bits of r/m8 right once d0 /1 C u C C C C C C C r rotate 8 bits or r/m8 right cl times d2 /1 C rotate 8 bits or r/m8 right imm8 times c0 /1 data 8 rotate 16 bits of r/m8 right once d1 /1 C rotate 16 bits or r/m8 right cl times d3 /1 C rotate 16 bits or r/m8 right imm8 times c1 /1 data 8 sahf store ah in low byte of the status flags reg 9e C C C C C C r r r r r
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 138 of 146 1 - 888 - 824 - 4184 tabl e 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c sal/shl multiply r/m8 by 2, once d0 /4 C u C C C C r r r r multiply r/m8 by 2, cl times d2 /4 C multiply r/m8 by 2, imm8 times c0 /4 data 8 multiply r/m16 by 2, once d1 /4 C multiply r/m16 by 2, cl times d3 /4 C multiply r/m16 by 2, imm8 times c1 /4 data 8 multiply r/m8 by 2, once d0 /4 C multip ly r/m8 by 2, cl times d2 /4 C multiply r/m8 by 2, imm8 times c0 /4 data 8 multiply r/m16 by 2, once d1 /4 C multiply r/m16 by 2, cl times d3 /4 C multiply r/m16 by 2, imm8 times c1 /4 data8 sar perform a signed division of r/m8 by 2, once d0 /7 C u C C C r r u r r perform a signed division of r/m8 by 2, cl times d2 /7 C perform a signed division of r/m8 by 2, imm8 times c0 /7 ib data 8 perform a signed division of r/m16 by 2, onc e d1 /7 C perform a signed division of r/m16 by 2, cl times d3 /7 C perform a signed division of r/m16 by 2, imm8 times c1 /7 data 8 sbb subtract imm8 from al with borrow 1c ib C r C C C r r r r r subtract imm16 from ax wi th borrow 1d iw - subtract imm8 from r/m8 with borrow 80 /3 ib subtract imm16 from r/m16 with borrow 81 /3 iw subtract sign - extended imm8 from r/m16 with borrow 83 /3 ib subtract byte reg from r/m8 with borrow 18 /r - subtract word reg from r/m16 with borrow 19 /r C subtract r/m8 from byte reg with borrow 1a /r C subtract r/m8 reg from word reg with borrow 1b /r - scas compare byte al to es:[di]; update di ae C C r C C C r r r r r compare word al to es:[di]; update di af C C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 139 of 146 1 - 888 - 824 - 4184 table 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c scasb compare byte al to es:[di]; up date di ae C C scasw compare word al to es:[di]; update di af C C shr divide unsigned of r/m8 by 2, once d0 /5 C u C C C r r u r 0 divide unsigned of r/m8 by 2, cl times d2 /5 C divide unsigned of r/m8 by 2, imm8 times c0 / 5 data 8 divide unsigned of r/m16 by 2, once d1 /5 C divide unsigned of r/m16 by 2, cl times d3 /5 C divide unsigned of r/m16 by 2, imm8 times c1 /5 data 8 ss ss segment reg override prefix 36 C C C C C C C C C C C stc set the carry flag to 1 f9 C C C C C C C C C 1 std set the direction flag so the source index (si) and/or the destination index (di) regs will decrement during string instructions fd C C C 1 C C C C C C C sti enable maskable interrupts after the next instruction fb C C C C 1 C C C C C C stos store al in byte es:[di]; update di aa C C C C C C C C C C C store ax in word es:[di]; update di ab C C stosb store al in byte es:[di]; update di aa C C stosw store ax in word es:[di]; u pdate di ab C C sub subtract imm8 from al 2c ib C r C C C r r r r r subtract imm16 from ax 2d iw C subtract imm8 from r/m8 80 /5 ib subtract imm16 from r/m16 81 /5 iw subtract sign - extended imm8 from r/m16 83 / 5 ib subtract byte reg from r/m8 28 /r C subtract word reg from r/m16 29 /r C subtract r/m8 from byte reg 2a /r C subtract r/m16 from word reg 2b /r C test and imm8 with al a8 ib C 0 C C C r r u r 0 a nd imm16 with ax a9 iw C and imm8 with r/m8 f6 /0 data 8 and imm16 with r/m16 f7 /0 iw and byte reg with r/m8 84 /r C and word reg with r/m16 85 /r - wait performs a n nop 9b C C C C C C C C C C C
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 140 of 146 1 - 888 - 824 - 4184 tabl e 9 7 . instruction set summary (continued) instruction opcode - hex flags affected mnemonic description byte 1 b yte 2 b yte s 3 C 6 o d i t s z a p c xchg exchange word reg with ax 90 +rw C C C C C C C C C C C exchange ax with word reg C C exchange byte reg with r/byte 86 /r C exchange r/m8 with byte reg /r C exchange word reg with r/m16 87 /r C exchange r/m16 with word reg /r C xlat set al to memory byte segment :[bx+unsigned al] d7 C C C C C C C C C C C xlatb set al to memory byte ds :[bx+unsigned al] d7 C C xor xor imm8 with al 34 ib C 0 C C C r r u r 0 xor imm16 with ax 35 iw C xor imm8 with r/m8 80 /6 ib xor imm16 with r/m16 81 /6 iw xor sign - extended imm8 with r/m16 83 /6 ib xor byte reg with r/m8 30 /r C xor word reg with r/m16 31 /r C xor r/m8 with byte reg 32 /r C xor r/m16 with word reg 33 /r C 7.1 key to abbreviations used in instruc tion set summary table abbreviations used in the instruction set summary table are explained below. 7.1.1 operand address byte the operand address byte is configured as shown below. 7 6 5 4 3 2 1 0 mod field aux f ield r/m field 7.1.2 modifier field the modifier field is defined below. mod description 11 r/m is treated as a register field 00 disp = 0, disp - low and disp - high are absent, address displacement is 0 01 disp = disp - low sign - extended to 16 - bits, disp - high i s absent 10 disp = disp - high:disp - low
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 141 of 146 1 - 888 - 824 - 4184 7.1.3 auxiliary field the auxiliary field is defined below. aux if mod = 11 and word = 0 if mod = 11 and word = 1 000 al ax 001 cl cx 010 dl dx 011 bl bx 100 ah sp 101 ch bp 110 dh si 111 bh di note: when mod 11, depends on instruction . 7.1.4 r/m field the r/m field is defined below. r/m description 000 ea = (bx) + (si) + disp [where ea is the effective address] 001 ea = (bx) + (di) + disp 010 ea = (bp) + (si) + disp 011 ea = (bx) + (di) + disp 100 ea = (si) + disp 101 ea = (di) + disp 110 ea = (bp) + disp [except if mod = 00, then ea = disp - high:disp - low] 111 ea = (bx) + disp 7.1.5 displacement the displacement is an 8 - or 16 - bit value added to the offset portion of the address. 7.1.6 immediate bytes the immediate byt es consist of up to 16 bits of immediate data. 7.1.7 segment override prefix the segment override prefix is configured as shown below. 7 6 5 4 3 2 1 0 0 0 1 sr sr 1 1 0
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 142 of 146 1 - 888 - 824 - 4184 7.1.8 segment register the segment register is shown below. sr segment register 00 es 01 cs 10 ss 11 ds 7.2 explanation of notation used in instruction set summary table notation used in the instruction set summary table is explained below. parameter indication : the component of the left is the se gment for a component located in memory. the component on the right is the offset. :: the component of the left is concatenated with the component on the right. operand definition imm8 immediate byte: signed number between C 128 and 127 imm16 immediat e word: signed number between C 32768 and 32767 m operand in memory m8 byte string in memory pointed to by ds:si or es:di m16 word string in memory pointed to by ds:si or es:di r/m8 general byte register or a byte in memory r/m16 general word register or a word in memory 7.2.1 opcode opcode parameters and definitions are provided below. parameter definition /0 - /7 the auxiliary field in the operand address byte specifies an extension (from 000 to 111, i.e., 0 to 7) to the opcode instead of a register. th us, the opcode for adding (and) an immediate byte to a general byte register or a byte in memory is 80 /4 ib . this indicates that the second byte of the opcode is mod 100 r/m. /r the auxiliary field in the operand address byte specifies a register ra ther that an opcode extension. the opcode byte specifies which register, either byte size or word size, is assigned as in the aux code above. /sr this byte is placed before the instruction as shown in section 7.1.7 , segment override prefix . cb the byte following the opcode byte specifies the offset. cd the double word following the opcode byte specifies the offset and a segment.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 143 of 146 1 - 888 - 824 - 4184 cw the word following the opcode byte specifies an offset or segment. ib immediate byte 7.2.2 flags affected after instruction flags affected after instr uction are shown below. u undefined - unchanged r result - dependent
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 144 of 146 1 - 888 - 824 - 4184 8. innovasic/amd part number cross - reference table table 98 . innovasic/amd part number cross - reference amd part number (e.g. am186er - 25kc \ w) innovasic part number 1 package 2 grade device type speed grade grade/package type ia18 x erpqf100ir 2 100 - lead pqfp, rohs compliant industrial am186er and am188er 25, 33, 40, 50 kc \ w, ki \ w 3 ia18 x er p l q100ir 2 100 - lead lqfp , rohs compliant industrial am186er and am188er 25, 33, 40, 50 vc \ w, vi \ w 4 vd \ w, vf \ w notes: 1. innovasics part number for these devices is marked as 18x to indicate the same device will be ordered for the 186 and 188 versions of th at particular package style. plea se refer to this data sheet for specific use of the pins for the 186 and 188 versions. 2. innovasic is offering the er in only rohs complaint packages. 3. amd did not offer the pqfp in a rohs compliant package. customers desirin g a replacement must switch to the r ohs c ompliant package. 4. customers desiring a replacement for the non - rohs lqfp must switch to the rohs compliant package.
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 145 of 146 1 - 888 - 824 - 4184 9. revision history table 9 9 includes the sequence of revisions to document ia 211110517 . table 99 . revision history date revision description page(s) october 10 , 2012 00 initial release na december 12, 2012 01 added min and max tolerances for lqfp package dimensions 22 february 25, 2013 02 changed document number from eng 211110517 to ia211110517 to signify production release all corrected innovasic p art n umbers 144
ia 186er/ia188er data s heet 16 - bit/ 8 - bit microcontrollers with ram february 25, 2013 ia211110517 - 0 2 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 146 of 146 1 - 888 - 824 - 4184 10. for additional information the innovasic support team wants its information to be complete, accurate, useful, and easy to understand. please feel free to contact experts at innovasic with sugg estions, comments, or questions at any time . innovasic support team 5635 jefferson st. ne, suite a albuquerque, nm 8710 9 usa phone: +1 - 505 - 883 - 5263 (international) fax: +1 (505) 883 - 5477 toll free: (888) 824 - 4184 (in us) e - mail: support@innovasic.com website: http://www.innovasic.com

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